The display subsystem consists of a graphics controller ASIC and 32 MB of DDR RAM on the main logic board. The graphics controller IC is an NVIDIA GeForce2 MX. It contains 2D and 3D acceleration engines, front-end and back-end scalers, a display controller, and an AGP 2x bus interface with bus master capability.
The graphics IC supports a display size of 1024 by 768 pixels. The graphics IC also has a scaling mode that displays a 640-by-480 or 800-by-600 pixel image on the full screen.
The display generated for the flat panel display is simultaneously available for an external monitor. See "Video Monitor Port".
The interface between the graphics IC and the rest of the system is an AGP (accelerated graphics port) 2x bus on the Pangea IC. To give the graphics IC fast access to system memory, the AGP bus has separate address and data lines and supports deeply pipelined read and write operations. The AGP bus has 32 data lines and a clock speed of 66 MHz.
The graphics IC uses a graphics address remapping table (GART) to translate AGP logical addresses into physical addresses. The graphics driver software can allocate memory in both the dedicated DDR RAM and the main memory.
For information about the display and supported resolutions, see "Flat Panel Display" and "Video Monitor Port".