UniNorth-2 (U1.5/2) Performance Counter Event List

The U1.5 and U2 North bridge chipsets contain four independent counters, each of which can count any one of 55 different types of events.

The table lists the events alphabetically by name, followed by the Event Number that must be selected to activate counting of a particular event. Some of the events are suffixed with a term in braces at the end of the event name. for example: If the term is [AGP], then the event can only occur if the AGP event source is active. If an event has no suffix, it can be generated by any active event source. The events suffixed with [Bus] are never generated by any of the sources, only by the front-side bus activities.

For more information, see “U1.5/U2 North Bridges.”

Performance Counter Event Name	Event Number
Addr-only Xacts Not Retried [Bus]	93
AGP R/W Hit Closed Page [AGP]	49
AGP R/W Hit Open Page [AGP]	48
AGP R/W Miss Open Page [AGP]	50, 100
AGP Read Hit Closed Page [AGP]	52
AGP Read Hit Open Page [AGP]	51
AGP Read Miss Open Page [AGP]	53, 101
All Xacts [Bus]	90
Burst Mem Reads [Bus]	88
Burst Mem Reqs [Bus]	77
Burst Mem Writes [Bus]	89
Burst PCI Reads [Bus]	84
Burst PCI Reqs [Bus]	76
Burst PCI Writes [Bus]	85
Burst Read Reqs [Bus]	72
Burst Write Reqs [Bus]	73
Burst Xacts [Bus]	65
Cache Inhib. Xacts [Bus]	91
Cycles Addr Bus Busy [Bus]	94
Cycles Data Bus Busy [Bus]	95
MaxBus Cycles [---]	1
Mem Read Reqs [Bus]	80
Mem Requests [Bus]	67
Mem Write Reqs [Bus]	81
PCI Read Reqs [Bus]	78
PCI Requests [Bus]	66
PCI Write Reqs [Bus]	79
R/W Hit Closed Page [Mem]	17
R/W Hit Open Page [Mem]	16
R/W Miss Open Page [Mem]	18
R/W Miss Open page [Mem]	39
R/W Page Hit (LRU) [Mem]	28
R/W Page Hit (MRU) [Mem]	27
Read Hit Closed Page [Mem]	30
Read Hit Open Page [Mem]	29
Read Miss Open page [Mem]	40
Read Miss Open Page [Mem]	31
Read Prefetch Buff Hits [Mem]	99
Read Prefetch Ops [Mem]	98
Read Xacts [Bus]	69
Retries on Maxbus [Bus]	97
Single Beat Mem Reads [Bus]	86
Single Beat Mem Reqs [Bus]	75
Single Beat Mem Writes [Bus]	87
Single Beat PCI Reads [Bus]	82
Single Beat PCI Reqs [Bus]	74
Single Beat PCI Writes [Bus]	83
Single Beat Read Reqs [Bus]	70
Single Beat Write Reqs [Bus]	71
Single Beat Xacts [Bus]	64
Sync/Eieio Not Retried [Bus]	92
UniN Retries on Maxbus [Bus]	96
Write Xacts [Bus]	68

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