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The data storage for the backside L2 cache consists of 1 MB of fast static RAM on the processor module. The controller and tag storage for the backside cache are built into the microprocessor. The cache controller includes bus management and control hardware that allows the cache to run at a sub-multiple of the processor's clock speed, rather than at the clock speed of the main system bus. The ratio of the clock speeds of the microprocessor and the backside cache is 5:2.