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Electrical Design of the RAM SO-DIMM

The electrical characteristics of the RAM SO-DIMM are given in section 4.5.6 of the JEDEC Standard 21-C, release 7. The specification is available from the Electronics Industry Association's web site, at

http://www.jedec.org/download/default.htm

The specification defines several attributes of the DIMM, including storage capacity and configuration, connector pin assignments, and electrical loading. The specification supports SO-DIMMs with either one or two banks of memory.

The JEDEC specification for the SO-DIMM defines a Serial Presence Detect (SPD) feature that contains the attributes of the module. SO-DIMMs for use in the iBook are required to have the SPD feature. Information about the required values to be stored in the presence detect EEPROM is in section 4.1.2.5 and Figure 4.5.6-C (144 Pin SDRAM SO-DIMM, PD INFORMATION) of the JEDEC standard 21-C specification, release 7.

Because the SO-DIMM connector has only two clock lines, and each clock line is limited to only 4 loads, an SO-DIMM with more than 8 SDRAM devices must have buffers on the clock lines. The buffers must be zero-delay type, such as phase-lock loop (PLL), which regenerates the clock signals. For example, the computer can support a 128-MB SO-DIMM using 16 devices and a PLL clock buffer.

SDRAM Devices

Configuration of RAM SO-DIMMs

Address Multiplexing


© 1999-2000 Apple Computer, Inc. – (Last Updated 15 Feb 00)

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