Hard Disk Connector

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Hard Disk Connector

The internal hard disk has a 48-pin connector that carries both the ATA signals and the power for the drive. The connector has the dimensions of a 50-pin connector, but with one row of pins removed, as shown in Figure 3-4. The remaining pins are in two groups: pins 1–44, which carry the signals and power, and pins 46–48, which are reserved. Pin 20 has been removed, and pin 1 is located nearest the gap, rather than at the end of the connector.

Figure 3-4 Hard disk connector and location

"Signal Assignments"

"ATA Signal Descriptions"

Signal Assignments

Table 3-5 shows the signal assignments on the 44-pin portion of the hard disk connector. A slash (/) at the beginning of a signal name indicates an active-low signal.

Table 3-5 Pin assignments on the ATA hard disk connector

Pin number	Signal name	Pin number	Signal name
1	/RESET	2	GROUND
3	DD7	4	DD8
5	DD6	6	DD9
7	DD5	8	DD10
9	DD4	10	DD11
11	DD3	12	DD12
13	DD2	14	DD13
15	DD1	16	DD14
17	DD0	18	DD15
19	GROUND	20	KEY
21	DMARQ	22	GROUND
23	/DIOW	24	GROUND
25	/DIOR, /HDMARDY, HSTROBE	26	GROUND
27	IORDY, /DDMARDY, DSTROBE	28	CSEL
29	/DMACK	30	GROUND
31	INTRQ	32	/IOCS16
33	DA1	34	/PDIAG, /CBLID
35	DA0	36	DA2
37	/CS0	38	/CS1
39	/DASP	40	GROUND
41	+5V LOGIC	42	+5V MOTOR
43	GROUND	44	Reserved

CSEL, /DASP, /IOCS16, and /PDIAG are not used; see Table 3-6.

ATA Signal Descriptions

Table 3-6 describes the signals on the ATA hard disk connector.

Table 3-6 Signals on the ATA hard disk connector

Signal name	Signal description
DA(0–2)	Device address; used by the computer to select one of the registers in the ATA drive. For more information, see the descriptions of the CS0 and CS1 signals.
DD(0–15)	Data bus; buffered from IOD(16–31) of the computer's I/O bus. DD(0–15) are used to transfer 16-bit data to and from the drive buffer. DD(8–15) are used to transfer data to and from the internal registers of the drive, with DD(0–7) driven high when writing.
/CBLID	The host checks this signal after Power On or hardware reset to detect whether an 80-conductor cable is present.
/CS0	Register select signal. It is asserted low to select the main task file registers. The task file registers indicate the command, the sector address, and the sector count.
/CS1	Register select signal. It is asserted low to select the additional control and status registers on the ATA drive.
CSEL	Cable select; not available on this computer (n.c.).
/DASP	Device active or slave present; not available on this computer (n.c.).
/DDMARDY	Drive ready to receive Ultra DMA data.
/DIOR	I/O data read strobe.
/DIOW	I/O data write strobe.
/DMACK	Used by the host to initiate a DMA transfer in response to DMARQ.
DSTROBE	Strobe for Ultra DMA data transfers to host.
/HDMARDY	Ultra DMA data ready.
HSTROBE	Strobe for Ultra DMA data transfers from host.
IORDY	I/O ready; when driven low by the drive, signals the CPU to insert wait states into the I/O read or write cycles.
/IOCS16	I/O channel select; not used on this computer.
DMARQ	Asserted by the device when it is ready to transfer data to or from the host.
INTRQ	Interrupt request. This active high signal is used to inform the computer that a data transfer is requested or that a command has terminated.
/PDIAG	Asserted by device 1 to indicate to device 0 that it has completed the power-on diagnostics; not available on this computer (n.c.).
/RESET	Hardware reset to the drive; an active low signal.
Key	This pin is the key for the connector.

The built-in ATA devices are connected to the I/O bus through bidirectional bus buffers.