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The Power Mac G4 has two PCI buses. The first PCI bus is a 66-MHz, 32-bit bus from the Uni-N IC. The second PCI bus is a 33-MHz, 64-bit bus to the KeyLargo I/O controller and the PCI slots. The PCI-PCI bridge IC provides the conversion between the two PCI buses. The rationale behind this arrangement has to do with reducing the number of pins on the Uni-N IC.
The PCI-to-PCI bridge IC is a DEC 21154-66 device. In addition to bridging between the two PCI buses, it provides performance enhancing features such as write buffering, memory read-ahead buffering, and transaction optimization.
The PCI-to-PCI bridge IC also provides arbitration for the 33 MHz secondary PCI bus. This arbiter is a two-tier round-robin arbiter. The low-priority tier gets one slot in the high-priority round-robin arbitration scheme. Placement of devices in the arbitration scheme is under software control, so any device may be placed in either the high-priority tier or the low-priority tier. For more details of the arbiter, see the DEC 21154-66 databook.