The ATI RAGE 128 PRO graphics controller IC on the accelerated graphics card contains the logic for the video display. The ATI RAGE 128 PRO graphics controller includes the following features:
A separate data bus handles data transfers between the ATI RAGE 128 PRO graphics controller and the display memory. The display memory data bus is 128 bits wide, and all data transfers consist of 128 bits at a time. The RAGE 128 PRO IC breaks each 128-bit data transfer into several pixels of the appropriate size for the current display mode--4, 8, 16, 24, or 32 bits per pixel.
The ATI RAGE 128 PRO graphics controller uses several clocks. Its transactions are synchronized with the AGP bus. Data transfers from the frame-buffer RAM are clocked by the MEM_CLK signal. Data transfers to the CLUT and the video output are clocked by the dot clock, which has a different rate for different display monitors.
The 2D graphics accelerator is a fixed-function accelerator for rectangle fill, line draw, polygon fill, panning/scrolling, bit masking, monochrome expansion, and scissoring.