The Pangea memory and I/O device controller IC combines several functions into a single IC. It contains the memory controller, the PCI bus bridge, the Ethernet and FireWire interfaces, the USB interface, and the AGP interface.
In addition to the buses listed in Table 2-1, the Pangea IC also has separate interfaces to the physical layer (PHY) ICs for Ethernet and FireWire and an I2C interface that is used for configuring the memory subsystem.
The Pangea IC provides DB-DMA (descriptor-based direct memory access) support for the I/O channels. The DBDMA system provides a scatter-gather process based on memory resident data structures that describe the data transfers. The DMA engine is enhanced to allow bursting of data files for improved performance.
The Pangea IC has an interrupt controller (Open-PIC) that handles interrupts generated within the IC as well as external interrupts, such as those from the Ethernet and FireWire controllers.
The following sections describe the subsystems that are connected to the Pangea IC.