I/O Operations and Memory
Several aspects of the operating system, the main processor, cache memory, and the memory hardware must be coordinated when an I/O operation is performed between an external device and a buffer in system memory:
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Memory protection: The I/O operation must not violate the access restrictions of the buffer.
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Residency: The I/O operation must not generate unsafe page faults when accessing the buffer. Typically a buffer must have physical memory assigned to it for the duration of the I/O operation.
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Addressability: When using DMA hardware to perform an I/O operation, it is necessary to convert a logical buffer specification into a physical specification. When using programmed I/O, it is necessary to convert the buffer specification (either logical or physical) to a logical specification that is addressable regardless of the current address space.
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Memory coherency: Coherency ensures that the data being moved is not stale and that the effects of the data movement are apparent to the processor and any associated data caches. Guaranteed coherency potentially applies to cache operations before and after the I/O operation.
The DSL provides services that ensure this coordination. One service assigns physical memory to the buffer, generates an appropriate buffer specification, and performs all necessary cache manipulations prior to the I/O operation. Another routine cleans up following the I/O operation. These services operate according to the computer's cache topology, taking into account whether the caches are logical or physical and whether the overall hardware architecture guarantees coherency. This shields drivers from having to compensate for the system memory architecture.
© 1999 Apple Computer, Inc. – (Last Updated 26 March 99)
