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This section describes the actions that the Macintosh Open Firmware performs on the PCI configuration registers listed in Figure 4-1 during startup.
The Vendor ID register is read and its value stored in the property vendor-id. If the card has no FCode, the Vendor ID value makes up the xxxx portion of the "pci xxxx,yyyy" default name property for the node.
The Device ID register is read and its value stored in the property device-id. If the card has no FCode and no subsystem ID, the Device ID value makes up the yyyy portion of the "pci xxxx,yyyy" default name property for the node.
The following bits in the Command register are set with the meanings shown:
The following bits are read in the Status register:
The value of bits 10-9, DEVSEL Speed, is stored in the node's devsel-speed property.
The value of bit 7, Fast Back-to-Back Capable, is noted for each PCI device. If the value is nonzero, the property fast-back-to-back is created for the node. See the previous section for information about the Fast Back-to-Back Enable bit.
No specific action is taken for the remaining bits in the Status register.
The Cache Line Size register is set for all devices as specified in the PCI Specification 2.1. This value may change from Macintosh platform to Macintosh platform for various performance reasons.
The Latency Timer register is set for all devices as specified in the PCI Specification 2.1. This value may change from Macintosh platform to Macintosh platform for various performance reasons.
The Header Type register is read, starting with bits 6-0. If the value of bits 6-0 is 0x00, the configuration space has a standard header layout for configuration addresses 0x10 through 0x3F; if the value is 0x01, it has a PCI-to-PCI bridge header layout for that section.
If FCode is present in the card's expansion ROM, the system Open Firmware creates an assigned-addresses property for the node, provided the card's FCode presents a reg property with entries referencing at least one base register and the system was able to provide the resources requested in the reg property corresponding to the base registers referenced. For each base register that has a corresponding entry in the assigned-addresses property, the system Open Firmware programs that base register with the address value stored in the assigned-addresses property.
If FCode is not present for the node, the system Open Firmware creates a reg property for the device. To create a reg entry for each base register that is implemented, the system Open Firmware writes all 1s to each base register location. It then reads the locations to see how many of the 1s are still there. If the register reads back as all 0s, then the register is not implemented and a reg entry is not made for it. If the register contains a value other than 0, the system Open Firmware notes which bits are 1s and thereby determines whether the register is of type memory or I/O, the amount of address space required, whether it is a 64-bit address, whether it is prefetchable, and whether it must be located below 1 MB. This information is then encoded appropriately into the reg entry for the base register. After all base registers are queried in this manner, the full reg property is stored in the device's node. Refer to the PCI specification and PCI Bus Binding to IEEE 1275-1994 (described in Other Publications ) for more details. Once the reg property is stored in the node, Open Firmware clears the Base registers to all 0s. It then follows the process of writing the registers with assigned-addresses values, as described above for devices that have FCode.
If the value of the Subsystem Vendor ID register is nonzero, a subsystem-vendor-id property is created with the register's value. If the property is created and no FCode is present on the card, the Subsystem Vendor ID value makes up the xxxx portion of the "pci xxxx,yyyy " default name property for the node.
The Subsystem Vendor ID register is described in Revision 2.1 of the PCI Specification.
If the value of the Subsystem ID register is nonzero and a subsystem-vendor-id property exists for the device, a subsystem-id property is created with the register's value. If the property is created and no FCode is present on the card, the Subsystem Vendor ID value makes up the yyyy portion of the "pci xxxx,yyyy " default name property for the node.
The Subsystem ID register is described in Revision 2.1 of the PCI Specification.
The system Open Firmware uses the Expansion ROM Base register at probe time to determine whether a card has FCode present. It queries the register to see whether the register is implemented, following the procedure described above for other base registers. If the register is implemented, Open Firmware temporarily maps in an amount of memory space equal to the requirement found from the base register query and then programs that value into the base register. It also enables the expansion ROM by an OR operation with 1 on bit 0 of the register and enables the card's memory space by writing a 1 to the correct bit in the Command register. It then reads the expansion ROM's first locations, by accessing the space temporarily mapped in, looking for the PCI signature (0x55AA). If it finds the signature, it continues to look for an Open Firmware ROM image signature. If it finds that signature, it locates the FCode, copies it to RAM, and executes it. After the card's FCode has finished executing, or if it was determined that there was no FCode, the system Open Firmware disables the card's memory space and expansion ROM and clears the Expansion ROM Base register to 0s.
If FCode was present in the card's expansion ROM and the FCode presented a reg property with an entry for the Expansion ROM Base register, and if the system was able to provide the resources for this entry, then the system Open Firmware creates a corresponding entry in the assigned-addresses property and writes the address value to the Expansion ROM Base register.
If FCode is not present for the node, the system Open Firmware creates a reg property for the device and determines whether to create an entry for the Expansion ROM Base register following the procedure for other base registers described above. The procedure for writing the register if FCode is present is the same as that in the preceding paragraph.
Bit 0 of the Expansion ROM Base register, which is defined as the Expansion ROM Enable bit, is left as 0 (disabled) by the system Open Firmware. If the run-time driver is interested in accessing the PCI Expansion ROM, it must first check that it has received an assigned-addresses entry, and then it must enable both its memory space (Memory Space Enable bit of the Command register) and its ROM (Expansion ROM Enable bit of the Expansion ROM Base register). As with all writable configuration registers, such operations must be performed with read-modify-write code sequences so as not to disturb the existing values of other bits in the registers.
No action is taken on the Interrupt Line register. It has no meaning for Power Macintosh computers because interrupts are OR-combined per slot in hardware, creating a unique interrupt for each PCI card accessible to the system interrupt controller. This register contains no useful information for drivers.
The Interrupt Pin register is read. If its value is nonzero, the value appears in the property interrupts. This register contains no useful information for drivers for the reasons explained in the previous section.