Register Settings
PCI-to-PCI bridges have specific configuration needs that are different from those of standard PCI devices. The system Open Firmware code is responsible for configuring the PCI-to-PCI bridge components. The following field descriptions list the standard settings for the registers shown in
Figure 4-2.
Field descriptions
-
Vendor ID
-
Read by Open Firmware and stored in the property
vendor-id.
-
Device ID
-
Read by system Open Firmware and stored in property
device-id.
-
Command
-
Written by system Open Firmware. Bit specifics:
-
Bit 9, Fast Back to Back Enable, is written 1 if all PCI devices are Fast Back to Back capable (if all devices have a
fast-back-to-back
property stored in their device nodes); otherwise written 0.
-
Bit 8, SERR Enable, is written 0 for all devices; the Power Macintosh system doesn't respond to SERRs.
-
Bit 7, Wait Cycle Control, is written 0 for all devices.
-
Bit 6, Parity Error Response, is written 0 for all devices.
-
Bit 5, VGA Palette Snoop, is written 0 for all devices.
-
Bit 4, Memory Write and Invalidate Enable. PCI-to-PCI Bridges consider this a read-only bit and will always return 0 when read. They act only as agents for masters behind them and will propagate Memory Write and Invalidate commands if a PCI Master on either side generates such a cycle.
-
Bit 3, Special Cycle Enable. PCI-to-PCI Bridges consider this a read-only bit and will always return 0 when read, because they cannot respond to Special Cycles.
-
Bit 2, Bus Master Enable, is written 1 for all devices; the Power Macintosh system supports masters in all PCI locations.
-
Bit 1, Memory Space Enable, is written 1 for PCI-to-PCI bridges to enable memory cycles to pass through the bridge transparently, based on the programming of the Memory Base and Limit registers.
-
Bit 0, I/O Space Enable, is written 1 for PCI-to-PCI bridges to enable I/O cycles to pass through the bridge transparently based on the programming of the I/O Base and Limit registers.
-
Status
-
The following bits are read in the
Status register:
-
Bits 10-9, DEVSEL speed, value stored in the node's
devsel-speed
property.
-
Bit 7, Fast Back to Back Capable, value noted for each PCI device. If the value is nonzero, the property
fast-back-to-back
is created for the node (see Command register explanation of Fast Back to Back Enable bit).
-
No specific action taken based on values of the remaining bits in the Status Register.
-
Revision ID
-
Read by system Open Firmware and stored in property
revision-id.
-
Class Code
-
Read by system Open Firmware and stored in property
class-code. The
name
property for PCI-to-PCI bridges defaults to
pci-bridg
e, based on the class code matching PCI-to-PCI bridge encoding (0x060400).
-
Cache Line Size
-
Written by system Open Firmware. Set to 0x08 for all devices, which corresponds to the PowerPC family cache line size of 32 bytes.
-
Latency Timer
-
Written by system Open Firmware. Set to 0x20 for all devices, which corresponds to 32 PCI clock intervals.
-
Header Type
-
Read by system Open Firmware. First, bits 6 through 0 are examined. If the value is 0x00, the configuration space has a standard header layout for configuration addresses 0x10-0x3F; if the value is 0x01, it has a PCI-to-PCI bridge header layout for that section. Described in this section is the behavior taken for a PCI-to-PCI header.
-
BIST
-
No action is taken by the system Open Firmware on this register.
-
base registers 0-1
-
Open Firmware does not set the Base Registers for PCI-to-PCI bridges. It is assumed that they are programmed only through PCI configuration space.
-
Primary Bus Number
-
Written by system Open Firmware with the appropriate PCI Bus number corresponding to this bridge's primary bus location (closer to main memory side) in the system topology.
-
Secondary Bus Number
-
Written by system Open Firmware with the appropriate PCI Bus number corresponding to this bridge's secondary bus location (farther from main memory side) in the system topology. This value is stored in the device tree as the first datum in the PCI-to-PCI Bridge's bus-range property.
-
Subordinate Bus Number
-
Written by system Open Firmware with the appropriate PCI Bus number corresponding to the highest numbered PCI bus that is located behind (subordinate to, or farthest from main memory) this PCI-to-PCI bridge. This value is stored in the device tree as the second datum in the PCI-to-PCI Bridge's bus-range property.
-
Secondary Latency Timer
-
Written by system Open Firmware. Set to 0x20 for all devices, which corresponds to 32 PCI clock intervals.
-
I/O Base
-
Written by system Open Firmware. If devices found behind the PCI-to-PCI bridge require I/O space address allocation, this byte-wide register is written with the appropriate values corresponding to the base of I/O space located behind the PCI-to-PCI bridge. See the PCI-to-PCI bridge architecture specification (described in
PCI Special Interest Group
) for details on this register. If no I/O space is requested behind the PCI-to-PCI Bridge, the I/O Base Register is written with a value greater than the I/O Limit value, thereby disabling any decoding of I/O space behind a PCI-to-PCI bridge.
-
I/O Limit
-
Written by system Open Firmware. If devices found behind the PCI-to-PCI bridge require I/O space address allocation, this byte-wide register is written with the appropriate values corresponding to the base of I/O space plus the amount of space required located behind the PCI-to-PCI bridge. See the PCI-to-PCI bridge architecture specification for details on this register. If no I/O space is requested behind the PCI-to-PCI Bridge, the I/O Base Register is written with a value greater than the I/O Limit value, thereby disabling any decoding of I/O space behind a PCI-to-PCI bridge.
-
Secondary Status
-
Read by Open Firmware. Bit specifics:
-
Bits 10-9, DEVSEL speed, the value stored in the node's
devsel-speed
property.
-
Bit 7, Fast Back to Back capable, a value set for each PCI device. If the value is non-zero, the property
fast-back-to-back
is created for the node (see Command register explanation of Fast Back to Back Enable bit).
-
No specific action is taken based on values of the remaining bits in the Secondary Status Register.
-
Memory Base
-
Written by system Open Firmware. If devices found behind the PCI-to-PCI bridge require memory space address allocation, this byte-wide register is written with the values corresponding to the base of memory space located behind the PCI-to-PCI bridge. See the PCI-to-PCI bridge architecture specification for details on this register. If no memory space is requested behind the PCI-to-PCI bridge, the Memory Base Register is written with a value greater than the Memory Limit value, thereby disabling any decoding of memory space behind a PCI-to-PCI bridge.
-
Memory Limit
-
Written by system Open Firmware. If devices found behind the PCI-to-PCI bridge require memory space address allocation, this byte-wide register is written with values corresponding to the base of memory space plus the amount of space required behind the PCI-to-PCI bridge. See the PCI-to-PCI bridge architecture specification for details on this register. If no memory space is requested behind the PCI-to-PCI bridge, the Memory Base Register is written with a value greater than the Memory Limit value, thereby disabling any decoding of memory space behind a PCI-to-PCI bridge.
-
Prefetchable Memory Base
-
Written by system Open Firmware. All memory space allocated behind a PCI-to-PCI bridge in PCI Power Macintosh systems is defined as non-prefetchable. Therefore, the Prefetchable Memory Base register is always written with a value that is greater than the Prefetchable Memory Limit value. This disables any decoding of Prefetchable Memory behind a PCI-to-PCI bridge.
-
Prefetchable Memory Limit
-
Written by system Open Firmware. All memory space allocated behind a PCI-to-PCI bridge is defined as non-prefetchable. Therefore, the Prefetchable Memory Base register is always written with a value that is greater than the Prefetchable Memory Limit value. This disables any decoding of Prefetchable Memory behind a PCI-to-PCI bridge.
-
Prefetchable Base Upper 32 bits
-
Written by system Open Firmware with all 0s, because the PCI Power Macintosh computers have a 32-bit address space.
-
Prefetchable Limit Upper 32 bits
-
Written by system Open Firmware with all 0s, because the PCI Power Macintosh computers have a 32-bit address space.
-
I/O Base Upper 16 bits
-
Written by system Open Firmware with all 0s, because the PCI Power Macintosh computers utilize a 16-bit I/O address space behind PCI-to-PCI bridges.
-
I/O Limit Upper 16 bits
-
Written by system Open Firmware with all 0s, because the PCI Power Macintosh computers utilize a 16-bit I/O address space behind PCI-to-PCI bridges.
-
Expansion ROM Base Register
-
Open Firmware takes no action with this register. It is assumed that PCI-to-PCI bridges have no FCode in their ROMs.
-
Interrupt Line
-
No action taken on this register. The value in this register has no meaning for the Power Macintosh computers, because interrupts are OR-combined per slot in hardware, creating a unique interrupt for each PCI card accessible to the system interrupt controller. No useful information for Power Macintosh driver writers exists in this register.
-
Interrupt Pin
-
Read by system Open Firmware. If the value is nonzero, it appears in the property
interrupts. It has no meaning for Power Macintosh, for the reasons given in the preceding paragraph.
-
Bridge Control
-
Written by system Open Firmware. Bit specifics:
-
Bit 7, Fast Back to Back Enable, is written 1 if all PCI devices on the secondary side of the PCI-to-PCI bridge are Fast Back to Back capable (if all devices have a fast-back-to-back property stored in their device node); otherwise, it is written 0.
-
Bit 6, Secondary Bus Reset, is written 0 so as not to cause a separate reset on the secondary bus from the regular PCI hardware reset, which is passed automatically by the PCI-to-PCI bridge hardware.
-
Bit 5, Master Abort Mode, is written 0 so that all Master Aborts on the Secondary bus return all Fs on read actions.
-
Bit 4, Reserved.
-
Bit 3, VGA Enable, is written 0, which disallows the forwarding of VGA hard decoding addresses to the secondary bus.
-
Bit 2, ISA Enable, is written 1, which blocks forwarding of traditional hard-decoded addresses (top 768 bytes for each 1K block of I/O space) from the primary to the secondary PCI bus.
-
Bit 1, SERR# Enable, is written 0, because the Power Macintosh system doesn't respond to SERR signals.
-
Bit 0, Parity Error Response, is written 0.
© 1999 Apple Computer, Inc. – (Last Updated 26 March 99)
