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> Power Macintosh G3 Developer Note
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PATHADC Home > Documentation > Hardware
> Power Macintosh G3 Developer Note
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The memory subsystem consists of RAM and ROM on the main logic board as well as the backside second-level (L2) cache, which is located on a separate card along with the microprocessor. The memory controller is described in Grackle Memory Controller and PCI Bridge IC .
The backside second-level (L2) cache consists of 512 KB or 1 MB of SRAM. The cache is on the microprocessor card. The clock frequency of the cache is programmable and runs at one half the speed of the microprocessor, a ratio of 2:1. The L2 cache clock frequency can be divided down by 1, 1.5, 2, 2.5, or 3 from the core operating frequency of the PowerPC G3 microprocessor.
With the NewWorld architecture, the system ROM consists of 1 MB of on-board ROM. It contains only the hardware specific code and tables needed to start up the computer, to load an operating system, and to provide common hardware access services. All the rest of the operaing system components that were formerly in ROM are now loaded from the boot device into RAM during the startup process. For a description of the ROM in the NewWorld architecture, refer to Boot ROM Contents .
Four DIMM sockets are used for main memory. The DIMM sockets support SDRAM devices on 168-pin JEDEC-standard 3.3-volt unbuffered PC-100 SDRAM DIMMs. Supported DIMM sizes are 8, 16, 32, 64, 128, and 256 MB. The Grackle IC provides memory control for the system RAM. For more information, see RAM DIMMs .
