Core ICs

The architecture of the main logic board is designed around five integrated circuits:

The computer also uses several standard ICs for I/O support, which include the Ultra DMA/33 controller, the FireWire controller, and the USB controller. This section describes only the core ICs.

Grackle Memory Controller and PCI Bridge IC

The Grackle IC functions as the bridge between the PowerPC microprocessor bus and the I/O and graphics devices on the PCI buses. It provides buffering and address translation from one bus to the other.

The Grackle IC also provides the control and timing signals for ROM and RAM. The memory control logic supports byte, word, longword, and burst accesses to the system memory. If an access is not aligned to the appropriate address boundary, Grackle generates multiple data transfers on the bus.

Memory Control

The Grackle IC controls the system RAM and ROM and provides address multiplexing and refresh signals for the DRAM devices. For information about address multiplexing, see RAM Address Multiplexing .

PCI Bus Bridges

The Grackle IC acts as a bridge between the processor bus and the PCI expansion buses, converting signals on the PCI bus to the equivalent signals on the processor bus and vice-versa. The PCI bridge functions are performed by two converters. One accepts requests from the processor bus and presents them to the PCI bus. The other converter accepts requests from the PCI bus and provides access to the RAM and ROM on the processor bus.

The PCI bus bridge in the Grackle IC runs synchronously. The processor bus operates at a clock rate of 100 MHz, the primary PCI bus operates at 66.67 MHz and the secondary PCI bus at 33.33 MHz. A Dec/Intel 21154 PCI-to-PCI bus bridge IC synchronizes transactions on the primary and secondary PCI buses for the Grackle IC. Primary PCI bus arbitration is performed by the Apple Gated Clocks II IC. The PCI-to-PCI bridge IC performs arbitration services for the secondary PCI bus.

The PCI bus bridge generates PCI parity as required by the PCI bus specification, but it does not check parity or respond to the parity error signal.

Paddington I/O Controller IC

The Paddington IC is an enhanced I/O controller and DMA engine for Power Macintosh computers using the PCI bus architecture. The Paddington IC in the Power Macintosh G3 is an improved version of the Paddington IC used in the iMac computer. The primary change is improved performance with 100 Mbps Ethernet. The changes are for internal operation and are transparent to software.

Paddington also provides power-management control functions for energy saving features included on Power Macintosh computers. The Paddington IC is connected to the secondary PCI bus and uses the 33 MHz PCI bus clock.

The Paddington IC includes circuitry equivalent to the Ethernet, ATA-3, SCC, and VIA controller ICs. The functional blocks in the Paddington IC include the following:

systemwide interrupt handling
ATA-3 interface controller
sound control logic and buffers
10/100 twisted-pair Ethernet controller

The Paddington IC provides bus interfaces for the following I/O devices:

56K modem card
VIA system interface to the Cuda IC
Burgundy sound input and output IC
64 KB nonvolatile RAM control

The Paddington IC also contains a serial interface and sound control logic for the Burgundy sound IC. The optional 56 Kbps modem uses the serial interface.

Burgundy Sound IC

The Burgundy sound IC combines a 16-bit digital sound encoder and decoder (codec). The Burgundy IC has the following sound controller features:

Digitizes analog inputs with internal analog to digital converters (A/Ds).
Creates analog outputs with internal digital to analog converters (DACs).
Facilitates digital audio routing between the inputs and outputs and CPU.
Provides digital gain, fade, balance, and mute controls.
Provides digital tone control.

For additional information about the audio features, see Sound System .

Graphics Controller IC

The ATI 3D RAGE 128 GL graphics controller IC on the accelerated graphics card contains the logic for the video display. The ATI 3D RAGE 128 GL graphics controller includes the following features:

advanced 128-bit rendering engine
architecture optimized to support high-speed SDRAM video memory
display memory controller, built-in drawing coprocessor, video scaler, color space converter, clock generator, and true color palette video DAC (digital-to-analog converter)
video CLUT (color lookup table)
hardware graphics acceleration with a 16-bit Z-buffer
accelerated QuickDraw 3D rendering up to six times that of software-only acceleration
true color palette DAC supporting pixel clock rates to 200 MHz for 1600 by 1200 resolution at 90 Hz
graphics and video line buffer for superior video scaling and playback quality
hardware cursor up to 64 x 64 x 2
DDC1 and DDC2B+ for plug-and-play monitor support
graphics control accessible through the QuickDraw, QuickDraw 3D, QuickDraw 3D RAVE, and QuickTime APIs

A separate data bus handles data transfers between the ATI 3D RAGE 128 GL graphics controller and the display memory. The display memory data bus is 64 bits wide, and all data transfers consist of 64 bits at a time. The RAGE IC breaks each 64-bit data transfer into several pixels of the appropriate size for the current display mode--4, 8, 16, 24, or 32 bits per pixel.

The ATI 3D RAGE 128 GL graphics controller IC uses several clocks. Its transactions are synchronized with the PCI bus. Data transfers from the frame-buffer RAM are clocked by the MEM_CLK signal. Data transfers to the CLUT and the video output are clocked by the dot clock, which has a different rate for different display monitors.

The 2D graphics accelerator is a fixed-function accelerator for rectangle fill, line draw, polygon fill, panning/scrolling, bit masking, monochrome expansion, and scissoring.