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Block Diagram and Buses

Figure 2-1 is a simplified block diagram of the Power Mac G4 computer. The diagram shows the main ICs and the buses that connect them together.

The architecture of the Power Mac G4 is based on the PowerPC G4 microprocessor and two custom ICs: the Uni-N memory controller and bus bridge, and the KeyLargo I/O controller.

The Power Mac G4 has four separate buses, not counting the processor's dedicated interface to the backside cache.

• Processor bus: 100-MHz, 64-bit bus connecting the processor module to the Uni-N IC

• Memory bus: 100-MHz, 64-bit bus connecting the main memory to the Uni-N IC

• AGP bus: 66 or 132-MHz, 32-bit bus connecting the AGP graphics card to the Uni-N IC

• PCI bus: 66-MHz, 32-bit bus connecting the boot ROM and the PCI-PCI bridge IC to the Uni-N IC ; 33-MHz, 64-bit bus connecting the KeyLargo I/O controller and the PCI slots to the PCI-PCI bridge IC

The remainder of this chapter describes the architecture in three parts centered around the processor module, the Uni-N memory controller and bridge IC, and the KeyLargo I/O controller IC.