This chapter describes the DDR SDRAM expansion features of the iMac G5 computer.
Note: For detailed instructions on accessing the expansion slots, refer to the iMac G5 Setup Guide that shipped with the computer or see the following Apple website: http://www.info.apple.com/usen/cip.
The main logic board of the iMac G5 computer has two DDR SDRAM expansion slots for unbuffered DDR400 (PC3200) dual in-line memory modules (DIMMs) for a maximum memory of 2 GB.
Each memory slot can contain 256 MB, 512 MB, or 1 GB of double data rate synchronous dynamic RAM (DDR SDRAM). The iMac G5 contains 256 MB of factory installed DIMM. The iMac G5 supports CAS latencies of 2, 2.5, 3, 4, and 5.
Additional DIMMs can be installed. The combined memory of all of the DIMMs installed is configured as a contiguous array of memory. The throughput of the 400 MHz memory bus is dependent on the DIMMs installed. If only one DIMM is installed, the memory bus is 64-bit. If two non-identical DIMMs are installed, there are two 64–bit memory buses. If two identical DIMMs are installed, the memory bus is 128-bit. Identical DIMM pairs have the same size and composition and provide the fastest and most efficient throughput.
Important: The user should be reminded to observe the usual precautions to avoid damage to the electronic components due to static electricity.
Warning: The computer must be turned off and unplugged before RAM modules are removed or inserted. To remind the user, a green LED is visible on the main logic board in the access door. If the green LED is on, power is on, and must be turned off before changing RAM modules.
The RAM expansion slots accept 184-pin DDR SDRAM DIMMs that are 2.5 volt, unbuffered, 8-byte, nonparity, and DDR400-compliant (PC3200). The iMac G5 only supports DIMMs up to 1.25” in height.
Important: DIMMs with any of the following features are not supported in the computer: registers or buffers, PLLs, ECC, parity, or EDO RAM.
The mechanical design of the DDR SDRAM DIMM is defined by the JEDEC specification JESD21-C, MODULES4_20_4, Release 11b. To find this specification on the World Wide Web, refer to “RAM Expansion Modules.”
The electrical design of the SDRAM DIMM is defined by the JEDEC specification JESD21-C, MODULES4_20_4, Release 11b. To find this specification on the World Wide Web, refer to “RAM Expansion Modules.”
The Serial Presence Detect (SPD) EEPROM specified in the JEDEC standard is required and must be set to properly define the DIMM configuration. The EEPROM is powered on 2.5 V. Details about the required values for each byte on the SPD EEPROM can be found on pages 68–70 of the JEDEC specification.
Important: For a DIMM to be recognized by the startup software, the SPD feature must be programmed properly to indicate the timing modes supported by the DIMM.
The largest DIMM supported is 1 GB. The maximum number of devices per DIMM is 16.
Important: Power is delivered to the iMac G5 during sleep mode, so do not remove DIMMs while in sleep mode. A green LED on the logic main board is illuminated when power is present.
Table 4-1 shows information about the different sizes of DDR SDRAM devices used in the memory modules. The memory controller supports 256 Mbit, 512 Mbit, and 1Gbit DDR SDRAM devices. The device configurations include three specifications: address range, word size, and number of banks. For example, a 1 M by 16 by 4 device addresses 1 M, stores 16 bits at a time, and has 4 banks.
The first column in Table 4-1 shows the memory size of the largest DIMM with that device size that the computer can accommodate. The third column specifies the number of devices needed to make up the 8-byte width of the data bus. The fourth column in the table shows the size of each bank of devices, which is based on the number of internal banks in each device and the number of devices per bank.
Signals A[0–12] on each SDRAM DIMM make up a 13-bit multiplexed address bus that can support several different sizes of SDRAM devices. Table 4-2 shows the address multiplexing modes used with the devices.
© 2000, 2007 Apple Inc. All Rights Reserved. (Last updated: 2007-04-03)