The U2 custom IC is at the heart of the Xserve computer. It provides the bridging functionality between the processor, the memory system, the PCI-based I/O system, the AGP graphics slot, and the FireWire and Ethernet interfaces.
Processor Bus
Main Memory Bus
Main PCI Bus
AGP/PCI Service
Boot ROM
Ethernet Controller
FireWire 400 and 800 Controllers
The processor bus is a 167 MHz, 64-bit bus connecting the processor module to the U2 IC. In addition to the increased bus clock speed, the bus uses MaxBus protocols, supported by the U2 IC, for improved performance.
The MaxBus protocol includes enhancements that improve bus efficiency and throughput over the 60x bus. The enhancements include
Out of order completion allows the memory controller to optimize the data bus efficiency by transferring whichever data is ready, rather than having to pass data across the bus in the order the transactions were posted on the bus. This means that a fast DRAM read can pass a slow PCI read, potentially enabling the processor to do more before it has to wait on the PCI data.
Address bus streaming allows a single master on the bus to issue multiple address transactions back-to-back. This means that a single master can post addresses at the rate of one every two clocks, as opposed to one every three clocks, as it is in the 60x bus protocol.
Intervention is a cache coherency optimization that improves performance for dual processor systems. If one processor modifies some data, that data first gets stored only in that processor’s cache. If the other processor then wants that data, it needs to get the new modified values. In previous systems, the first processor must write the modified data to memory and then the second processor can read the correct values from memory. With intervention, the first processor sends the data directly to the second processor, reducing latency by a factor of ten or more.
The main memory bus is a 167 MHz, 64-bit bus connecting the main memory to the U2 IC. Main memory is provided by up to four DDR333 SDRAM DIMMs. Supported DIMM sizes are 128, 256, and 512 MB. The memory slots will accept four 512-MB DIMMs for a maximum memory size of 2 GB. The minimum speed DDR is 2x167 MHz, which is DDR333 (PC2700).
For more information about memory DIMMs, see “RAM Expansion”.
The main PCI bus connects the U2 IC to the boot ROM, through one PCI-to-PCI bridge the KeyLargo I/O controller, and through a second PCI-to-PCI bridge to the PCI slots. The PCI slots support “universal” PCI cards with 33 or 66 MHz operation. The PCI bus is a 66-MHz, 64-bit bus for the highest possible PCI card performance.
The PCI bus also supports the Apple Drive Module (ADM) interfaces: dual 2-channel ATA/133 controllers.
The U2 IC used in the Xserve computer supports a new PCI feature called Write Combining. This feature allows sequential write transactions involving the Memory Write or Memory Write and Invalidate commands to be combined into a single PCI transaction. The memory write transactions being combined must be to sequential, ascending, and non-overlapping PCI addresses. Placing an eieio or sync command between the write commands will prevent any write combining.
In the slot load Xserve computer, a combination slot supports either a PCI or an AGP card through a personality slot video card. When used for PCI, it supports 66 MHz 32-bit only operation. When used for AGP, it supports a 4X AGP bus. This slot does not provide any ADC power. For further details, see “PCI Expansion Slots”.
The boot ROM consists of 1 MB of on-board flash EPROM. The boot ROM includes the hardware-specific code and tables needed to start up the computer. It uses Open Firmware to initialize the hardware, build the device tree, load an operating system, and provide common hardware access services.
The U2 IC includes an Ethernet media access controller (MAC). As a separate I/O channel on the U2 IC, it can operate at its full capacity without degrading the performance of other peripheral devices. The U2 IC provides DMA support for the Ethernet interface.
The MAC implements the link layer. It is connected to a PHY interface IC that provides 10-BaseT, 100-BaseT, or 1000-BaseT operation over a standard twisted-pair interface. The operating speed of the link is automatically negotiated by the PHY and the bridge or router to which the Ethernet port is connected. For information about the port, see “Ethernet Ports”.
The U2 IC includes an IEEE 1394a FireWire 400 controller that implements the FireWire 400 link layer, supporting a maximum data rate of 400 Mbits per second. And, the U2 IC includes an IEEE 1394b FireWire 800 controller that implements the FireWire 800 link layer, supporting a maximum data rate of 800 Mbits per second.
Two physical layer (PHY) ICs connected to the U2 IC implement the electrical signaling protocol for the FireWire ports. The FireWire 400 port is located on the front panel; two FireWire 800 ports are located on the back panel.
While the PHYs are operating, they act as repeaters so that the FireWire bus remains connected. For more information, see “FireWire Ports”.
| Note: The PHYs are powered as long as the computer is connected to AC power. |