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PowerPC Processor and PCI Commands

The PowerPC processor has a 64-bit data bus and its system memory space defaults to write back cache mode, while the PCI bus is 32-bits wide and the PowerPC processor sets PCI address space to cache inhibit mode. For PowerPC initiated read and write transactions between PCI memory space, the IB chip (the PowerPC Processor to PCI Bridge) will initiate basically one of the three following types of PCI commands:

1. a single-beat Memory Read or Write command;
2. a Memory Read or Write command with two data phases -- defined as a burst transaction;
3. a Memory Read Line or Memory Write and Invalidate command that bursts a 32-byte cache line.