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The guidelines in this section examine the PCI bus commands, the operation of the PowerPC processor to PCI interface bridge chip, achievable PCI bandwidth on PCI Power Macintosh computers, and finally, Mac OS services available to maximize PCI bandwidth.
A good place to start addressing PCI performance on Power Macintosh CPUs is the PCI standard itself. The PCI Bus Specification features a 32-bit data path -- upgradeable to 64-bits -- with synchronous bus operation up to 33 Mhz, and the ability to transfer a data object on the raising edge of each PCI clock cycle. Assuming that neither the initiator nor the target inserts wait states during each data phase, the maximum theoretical bandwidth over a 32-bit bus is 132 Mbytes/second. This also assumes continuous bursting with a 32-bit data object transferred on each PCI clock cycle. (Apple's implementation incorporates a 32-bit data bus.)
Because the IB chip competes for system memory along with other system devices, continuous PCI bursting is not possible. Therefore, the achievable PCI bandwidth on Power Macintosh computers is less than the PCI theoretical maximum. Also, the bandwidth is dependent on the PCI target's hardware design and the architecture of the driver software.
A PCI burst transfer is defined by one PCI bus transaction with a signal address phase followed by two or more data phases. One may ask, how can the bus master transfer a data object on each PCI clock cycle? To initiate a bus transaction, the PCI master only has to arbitrate for ownership of the bus one time. The master then issues the start address and transaction type during the address phase. It is the responsibility of the target device to latch the start address into an address counter and increment the addressing from data phase to data phase. (A single-beat read or write transaction is defined by a signal address phase followed by only one data phase.)
For data to be transferred between the PowerPC processor and the PCI target, or for the PCI target to transfer data between system memory, one of the commands shown in Table 1-4 is initiated.
Table 1-4 Commands between PowerPC processor and PCI bus
The I/O Read and I/O Write commands are used to transfer data between the PowerPC processor and the target's I/O space.
The Configuration Read and Configuration Write commands are used to transfer data between the PowerPC processor and the PCI target's configuration registers during system initialization.
The Memory Read and Memory Write commands are used to transfer data between the PCI Master and the target's memory space.
The Memory Read Line command is used by the PCI Master to transfer a cache line of data from the PCI target's memory space.
The Memory Read Multiple command is used by the PCI Master to transfer more than one cache line of data from the PCI Target's memory space.
The Memory Write and Invalidate command is used by the PCI Master to transfer one or more complete cache lines of data to the PCI target's memory space.
A cache line is 32-bytes for Apple Power Macintosh computers.