Bursting from PCI to PowerPC

If the address is aligned on an 8-byte boundary, the IB chip will respond to PCI Memory Read and Memory Write commands by a two-beat PCI transaction to align two 32-bit PCI data words to the 64-bit PowerPC bus. On non-8-byte-aligned addresses, single-beat transactions are implemented.

The PCI Memory Write and Invalidate command will perform an 8-beat transaction if the address is aligned on a 32-byte boundary.

The PCI Memory Read Line or Memory Read Multiple commands perform an eight-beat transaction if the address is aligned to an address less than or equal to 8-bytes less than the next 32-byte boundary. The PCI Memory Read Line and Memory Read Multiple commands are treated the same by the IB chip, in either command case the IB chip disconnects after an eight-beat transaction, which is one 32-byte cache line.

Note

Keep in mind that the main memory space is set to write back cache mode.

As mentioned earlier, 132 Mbytes/sec is the maximum theoretical bandwidth across a 32-bit PCI bus at 33 Mhz. Table 1-5 and Table 1-6 show the maximum achievable bandwidth that can be expected, depending on the type of PCI transaction performed. The values shown are not guaranteed, but are realistic ranges that have been measured moving large buffers (many thousands of bytes) to average out PCI arbitration PCI wait states across a Power Macintosh Computer's PCI bus.

The bandwidth performance numbers shown in Table 1-5 and Table 1-6 are based on the following assumptions:

Bus speed:

Processor Bus is running at minimally 40 Mhz
PCI Bus is running at 33 Mhz

PCI target responses during PowerPC processor to PCI transactions:

PCI targets are medium DevSel_ timing with NO inserted wait states for reads and writes.
PCI target does not assert Stop_ to disconnect bus.

PCI master requirements during PCI master with system memory transactions:

PCI master is able to source data within one clock of Frame_ assertion with no inserted wait states for subsequent data phases.
PCI master is able to sink data with no inserted wait states for subsequent data phases once the host bridge asserts Trdy_.
PCI master is able to start its next transaction within two clocks from the PCI bus returning to the Idle state from its previous transaction.

Table 1-5 PowerPC processor to PCI maximum bandwidth summary

Bus master	Transaction description	Bytes per transaction	PCI bandwidth, MB/s	PowerPC setup
Processor	Write To PCI	4	20	Integer Store
Processor	Write To PCI	8	40	Floating Point Store
Processor	Write To PCI	32	85	PCI Copyback
Processor	Read from PCI	4	11	Integer Load
Processor	Read from PCI	8	20	Floating point Load
Processor	Read from PCI	32	40	PCI WriteThru

Table 1-6 shows the PCI master to system memory bandwidth measurements for a 33 MHz PCI bus in a system with a 40 MHz processor bus.

Table 1-6 PCI master to system memory maximum bandwidth summary

PCI master	Transaction description	Bytes per transaction	PCI bandwidth, MB/s	PowerPC command
PCI master	Write to memory	4	20	Mem Write
PCI master	Write to memory	8	35	Mem Write
PCI master	Write to memory	32	80	Mem Write and Invalidate
PCI master	Read from memory	4	10	Mem Read
PCI master	Read from memory	8	15	Mem Read
PCI master	Read from memory	32	30	Mem Read line multiple

For number of bytes per transaction 4 indicates single-beat; 8 equals two-beats; and 32 is an 8-beat transaction.