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PCI Transaction Error Responses

The PCI host bridge responds to system error and exception conditions in a manner that prevents the system from hanging. The bridge tries to signal the error or exception and terminate the transaction gracefully. Buffers are made available for use after the exception or error. Error translations when the PCI host bridge acts as a PCI master (that is, as an agent for the PowerPC bus master) are shown in Table 1-7.

Table 1-7 Bridge master errors

Transaction	PCI target response	Result
Write	No DEVSEL (master abort)	Data discarded after posting. Received master abort error interrupt generated.
Write	Target abort	Data discarded after posting. Received target abort error interrupt generated.
Read	No DEVSEL (master abort)	Machine check exception (bus error) generated. Received master abort error interrupt generated.
Read	Target abort	Machine check exception (bus error) generated. Received target abort error interrupt generated.

Error translations when the PCI host bridge acts as a PCI target (that is, as an agent for the PowerPC bus target) are shown in Table 1-8.

Table 1-8 Bridge target errors

Transaction	PowerPC bus target response	Result
Write	Bus error	Data discarded after posting. Signaled target abort error interrupt generated (though target abort is not signaled because the write was already posted).
Read	Bus error	Generate target abort. Signaled target abort error interrupt generated.