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The PowerPC microprocessor supports a little-endian processing mode, in which addresses are swizzled when they are used to access memory. The swizzle applies an XOR operation to the low-order 3 bits of an address with a constant that depends upon the size of the data being loaded or stored. Word load and store actions use a value of 0b100, halves use 0b110, and bytes use 0b111. The resulting addresses are used to make memory references to a big-endian memory system.
The PowerPC's effective address is not modified, only the interpretation used to access memory. For example, the update forms of load and store instructions alter the base register with the same value, regardless of the current endian mode. Thus, the address swizzle is completely transparent to software.
Notice that the address swizzle in little-endian processing mode changes only the lower 3 bits. The number of address bits swizzled depends upon the maximum scalar data type that can be accessed by the system; it does not depend upon the width of the processor's data path. In the case of PowerPC processor, the longest scalar is a double word--hence, swizzling 3 bits suffices to transform any address.
By swizzling the offsets in the big-endian DMA descriptor value shown in Figure A-10, little-endian processing mode produces a new set of offsets. For example, the processor applies the calculation 0b000 XOR 0b100 to the 0 offset for the word field aDescr.A, producing the offset 0b100, or 4. Software can read the correct value of 0x44454647 at that offset. The result is that the whole descriptor appears to have the structure shown in Figure A-11.
Figure A-11 Descriptor swizzled by little-endian processing mode
PowerPC little-endian mode does not support misaligned data accesses. Access to misaligned data must be done by code sequences or subroutines. As is the case with byte-reversed load and store instructions, there is currently no compiler support for handling misaligned data.