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Symmetric Multiprocessing

In future Power Macintosh computers that feature symmetric multiprocessing (SMP), a device driver will not be able to assume that hardware or secondary interrupt level execution preempts all task level execution. In a four-processor system, for example, one processor might be running a hardware interrupt handler, another running a secondary interrupt handler, and the other two running tasks. This behavior is different from that of a uniprocessor system, where an interrupt handler normally runs to completion between two task-level instructions. The difference is illustrated in Figure 6-3.

Figure 6-3 Uniprocessing and multiprocessing execution

Symmetric multiprocessing changes some of the programming rules for driver writers. Observe these cautions:

• If you use an atomic operation to reference a particular memory location at task level (such as an atomic increment to a counter), you must also use atomic instructions when referencing that location at hardware and secondary interrupt level.
• If you disable interrupts and use secondary interrupt level following the rules in this book, you shouldn't have any problems. If you assume that no task can be running while your interrupt handler runs, your code will break on a multiprocessor system.
• If your driver disables interrupts for its device while running at task level, an interrupt for a different device can still occur. The second interrupt may run concurrently with your task-level device driver as shown in Figure 6-3.

Disabling hardware interrupts for synchronization purposes works safely in an SMP environment. Disabling hardware interrupts on one processor guarantees that interrupts are off on every processor and that no other processor can execute code that runs with interrupts off. If another processor tries to disable interrupts, it will loop while waiting for the first processor to turn interrupts on again. This feature makes it critical that interrupts be disabled for very short periods of time.

Similarly, in an SMP environment only one processor at a time can run at secondary interrupt level. Other processors trying to run at secondary interrupt level will do no useful work until the first processor exits that level. For this reason, secondary interrupt level should be used as sparingly as possible.