Microprocessor and Cache

The microprocessor communicates with the rest of the system by way of a 66-MHz, 64-bit 60x bus to the Uni-N IC. The microprocessor has a separate backside bus to its second-level cache.

G3 Microprocessor

The current family of PowerPC microprocessor designs is called "G3," for "generation three." The G3 microprocessors have several features that contribute to improved performance, including:

large on-chip (L1) caches, 32 KB each for instruction cache and data cache
a built-in cache controller and cache tag RAM for the L2 cache
a separate backside bus for the L2 cache, providing faster clock speed and overlapped bus transactions
a microprocessor core optimized for Mac OS applications

The G3 microprocessor in the iBook runs at a clock speed of 300 or 366 MHz.

Backside Cache

The data storage for the backside L2 cache consists of 512 KB of fast static RAM on the main logic board. The controller and the tag storage for the backside cache are built into the microprocessor chip. The cache controller includes bus management and control hardware that allows the cache to run at an independent sub-multiple of the processor's clock speed, rather than at the slower clock speed of the main system bus. In the iBook, the clock speed of the backside cache is related to that of the microprocessor as shown in Table 2-1.

Table 2-1 CPU and cache clock speeds

CPU clock	Cache clock	Ratio
300 MHz	150 MHz	2:1
366 MHz	146.4 MHz	5:2