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The Uni-N memory controller and bus bridge IC provides cost and performance benefits by combining many functions into a single IC. It contains the memory controller, the PCI bus bridge, the Ethernet interface, and the AGP port.
In addition to the four buses listed in Table 2-2, the Uni-N IC also has a separate interface to the physical layer (PHY) IC for Ethernet and an I2 C interface that is used for configuring the memory subsystem.
The microprocessor and the I/O controller IC are described in their own sections. The following sections describe the other subsystems that are connected to the Uni-N IC.
The memory subsystem in the iBook consists of 64 MB of SDRAM on the main logic board and one expansion slot for an SO-DIMM. (The original iBook had 32 MB of SDRAM and the slot.) The data bus to the RAM and DIMM is 64 bits wide, and the memory interface is synchronized to the 60x bus interface at 66 MHz. See also RAM Expansion.
The boot ROM is connected to the Uni-N IC by way of the PCI bus plus three additional control signals: chip select, write enable, and output enable. The boot ROM is a 1 M by 8 bit device.
The boot ROM is a flash device and can be updated in the field.
The Ethernet link layer is built into the Uni-N IC. The physical layer is a 5201 IC made by Broadcom. The 5201 IC contains both the physical layer and the transceiver and filter circuits. The IC provides a dual-speed Ethernet controller, supporting both 10Base-T and 100Base-TX protocols.
The graphics IC is a variation of the RAGE Mobility IC made by ATI. Certain features of the Mobility IC are not supported in this variation.
The graphics IC includes 4 MB of VRAM, which enables it to provide a display size of 800 by 600 at pixel depths of 8, 16, and 24 bits per pixel. The graphics IC also has a scaling mode that displays a 640-by-480 pixel image on the full screen.
Because it uses the AGP bus, the graphics IC can use part of main memory as additional graphics storage. The computer's virtual memory system organizes main memory as randomly-distributed 4 KB pages, so DMA transactions for more than 4 KB of data would have to perform scatter-gather operations. To avoid this necessity for graphics storage, the AGP logic in the Uni-N IC uses a graphics address remapping table (GART) to translate a linear address space for AGP transactions into physical addresses in main memory.