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Architecture

This chapter describes the architecture of the Power Mac G5 computer. It includes information about the major components on the logic boards: the microprocessor, the other main ICs, and the buses that connect them to each other and to the I/O interfaces.

In this section:

Block Diagram and Buses
Processor Module
U3 Bridge and Memory Controller
HyperTransport Technology
PCI USB Controller
K2 I/O Controller
Graphics Cards
Fan Controller

Block Diagram and Buses

Figure 2-1 is a simplified block diagram of the Power Mac G5 computer. The diagram shows the main ICs and the buses that connect them together.

The architecture of the Power Mac G5 computer is based on the PowerPC G5 microprocessor, and two custom ICs: the U3 memory controller and bus bridge and the K2 I/O controller.

The Power Mac G5 computer has the following data buses, not counting the processor’s dedicated interface to the backside cache.

• Processor bus: 800/900/1000 MHz, 64-bit (32-bit in and 32-bit out) data throughput per processor connecting the processor module to the U3 IC

• Dual processor systems have two independent 64-bit (32-bit in and 32-bit out) processor buses

• Memory bus: 333 or 400 MHz, 128-bit bus connecting the main DDR SDRAM memory to the U3 IC

• 8x AGP Pro bus: 266/533 MHz, 32-bit bus connecting the AGP graphics card to the U3 IC

• PCI or PCI-X bridge bus: supports three 64-bit PCI-X slots ( two 100 MHz and one 133 MHz) or three 33 MHz PCI slots

• Internal PCI bus: 33 MHz, 64-bit bus supports the K2 I/O controller, the boot ROM, the AirPort Extreme Card slot, and the USB controllers

• Serial ATA (S-ATA) buses: support 1.5 Gbps internal hard drive connectors

• Ultra DMA ATA/100 bus: supports internal optical drive

• HyperTransport: high-speed, bidirectional, point-to-point link for integrated circuits supports bidirectional data rates up to 3.2 GBps

The remainder of this chapter describes the architecture of the processor module, the U3 memory controller and bridge IC, the K2 I/O controller IC, and the USB controllers.

Processor Module

The processor module is a separate logic board that contains one PowerPC G5 microprocessor. Dual microprocessor configurations contain two identical PowerPC G5 processor modules.

The processor module is connected to the main logic board by a 300-pin connector. To achieve the required level of performance, the signal lines that connect the processor module and the main logic board are carefully matched in length, loading, and impedance.

PowerPC G5 Microprocessor

The PowerPC G5 used in the Power Mac G5 computer has the following features:

• 64-bit PowerPC implementation with 42-bit physical memory addressing

• core runs at twice the bus speed

• superscalar execution core supporting more than 200 in-flight instructions

• two independent double-precision floating point units

• Velocity Engine: 128-bit-wide vector execution unit

• 64K L1 instruction cache, 32K L1 data cache per processor

• fully symmetric multiprocessing capability

• built-in 512 KB backside L2 cache per processor

• two independent, unidirectional 800 MHz to 1 GHz frontside buses each supporting up to 8 GBps data throughput per processor

For more information, see the reference at “PowerPC G5 Microprocessor.”

U3 Bridge and Memory Controller

The U3 custom IC is at the heart of the Power Mac G5 computer. It provides the bridging functionality among the processors, the memory system, HyperTransport bus to the PCI-based I/O system, and the AGP slot.

Processor Bus

The processor bus is a 800 MHz, 900 MHz, or 1 GHz bus connecting the processor module to the U3 IC. The bus has 64-bit wide data and 36-bit wide addresses.

The Power Mac G5 system controller is built with the same state-of-the-art 130-nanometer, SOI technology as the PowerPC G5 processor. This super-efficient point-to-point architecture provides each subsystem with dedicated bandwidth to main memory. The Power Mac G5 uses separate processor boards with each PowerPC G5 processor; two processor boards are used for dual processor systems. The U3 I/O implements two independent processor interfaces. The processors range from 1600 to 2000 MHz in clock rate and connect to the U3 I/O through the Apple Processor Interface (API). The processor clock is derived from a PLL which multiplies the reference clock by preset intervals of 6 or 8 times.

Out-of-order completion allows the memory controller to optimize the data bus efficiency by transferring whichever data is ready, rather than having to pass data across the bus in the order the transactions were posted on the bus. This means that a fast DDR SDRAM read can pass a slow PCI read, potentially enabling the processor to do more before it has to wait on the PCI data.

Intervention is a cache-coherency optimization that improves performance for dual-processor systems. If one processor modifies some data, that data first gets stored only in that processor’s cache. If the other processor then wants that data, it needs to get the new modified values.

Main Memory Bus

The Power Mac G5 computer main memory bus connects the main memory to the U3 IC via the 64-bit data bus. The DDR SDRAM DIMM specifications for the standard configurations are shown in Table 2-1.

Standard supported DIMM sizes are 128, 256, and 512 MB, and capable of 1 GB. The DIMMs must be unbuffered and installed in pairs of the same size.

For more information about memory DIMMs and installation, see “RAM Expansion.”

Accelerated Graphics Port Bus

The accelerated graphics port (AGP 8x Pro) bus is a 266/533 MHz, 32-bit bus connecting the AGP card to the U3 IC. DDR data is transmitted at both edges of the clock for peak transfers of 2.1 GBps.

The AGP bus is an enhanced PCI bus with extra functionality to burst texture data and other graphics across the port up to 8 times faster than a 66 MHz PCI port. The Power Mac G5 computer’s AGP implementation is compatible with version 3 of the AGP specification and with the Pro version of AGP. AGP 3.0 enables deeply pipelined memory read and write operations and demultiplexing of address and data on the bus.

To further improve the performance of the AGP bus, the U3 IC supports a graphics address remapping table (GART). Because the virtual memory system organizes main memory as randomly distributed 4 KB pages, DMA transactions for more than 4 KB of data must perform scatter-gather operations. To avoid this necessity for AGP transactions, the GART is used by the AGP bridge in the U3 to translate a linear address space for AGP transactions into physical addresses in main memory.

For more information on the graphics cards installed in the AGP slot, refer to “Graphics Cards.”

Internal PCI Bus

An internal 33-MHz, 64-bit PCI bus connects the K2 I/O controller to the boot ROM, the AirPort Extreme Card slot, and the USB controller. The U3 IC used in the Power Mac G5 computer supports the PCI write combining feature. This feature allows sequential write transactions involving the Memory Write or Memory Write and Invalidate commands to be combined into a single PCI transaction. For memory write transactions to be combined, they must be sequential, ascending, and non-overlapping PCI addresses. Placing an eieio or sync command between the write commands prevents any write combining.

For more information on the PCI bus, refer to “PCI or PCI-X Expansion Slots.”

PCI or PCI-X Expansion Slots

The Power Mac G5 computer provides three PCI or PCI-X slots via the HyperTransport bus. In some configurations of the Power Mac G5, one slot runs at a maximum of 133 MHz and two slots run at a maximum of 100 MHz. In other configurations of the Power Mac G5 computer, all three slots run at 33 MHz. Each slot has room for a full size 12.335-inch or short 6.926-inch card. The slots are numbered from 2 to 4 on back panel, on the PCB, and in the Apple System Profiler. To satisfy cooling power supply requirements, a total of 90 W is allocated to the three PCI or PCI-X slots and the AGP Pro slot.

The connectors to the PCI or PCI-X slots are 3.3 V keyed and support 32-bit and 64-bit buses. The connectors include a PME signal which allows a PCI card to wake the computer from sleep.

The slots (12.335 inch) have a capture feature which is at the end of the slot. If a card exceeds the short length it is recommended that the long length be used rather than an intermediate length, to assure the card stays secure if and when the system is in shipment.

The 133 MHz slot can support a maximum burst bandwidth of 1064 MBps, based on 64 bits times 133 MHz. The two 100 MHz slots can support a combined bandwidth of 800 MBps. It is recommended that the highest bandwidth card be inserted in slot 4.

For more information, refer to “PCI or PCI-X Expansion Slots.”

Wireless LAN Module

The optional AirPort Extreme wireless LAN module connects via the PCI interface.

The AirPort Extreme Card wireless LAN module contains a media access controller (MAC), a digital signal processor (DSP), and a radio-frequency (RF) section. The module has an antenna port on the rear of the computer.

The AirPort Extreme Card is based on the IEEE 802.11g standard. The card transmits and receives data at up to 54 Mbps and is compatible with 802.11b-standard 11 Mbps systems and earlier 2 Mbps systems. For information about its operation, see “AirPort Extreme Card.”

The build-to-order Bluetooth connectivity comes off the K2 IC; see “Bluetooth Technology” for more information.

Modem Slot Support

The K2 IC supports the modem and provides DB-DMA (descriptor-based direct memory access) support for the modem slot interface.

The internal hardware modem is a separate module that contains a modem controller IC, a data pump, and the interface to the telephone line (DAA). For more information about the modem, see “Internal Modem.”

Boot ROM

The boot ROM consists of 1 MB of on-board flash EEPROM. The boot ROM includes the hardware-specific code and tables needed to start up the computer using Open Firmware, to load an operating system, and to provide common hardware access services.

HyperTransport Technology

The DDR HyperTransport is an advanced chip-to-chip communications technology that provides a high-speed, high-performance, point-to-point link for integrated circuits. HyperTransport provides a universal connection that reduces the number of buses within a system.

The HyperTransport bus between the U3 IC and the PCI-X bridge is 16 bits wide, supporting total of 3.2 GBps bidirectional throughput. Between the PCI-X bridge and the K2 IC, the bus width is 8 bits, supporting total of 1.6 GBps bidirectional throughput.

For more information on the HyperTransport technology, go to the World Wide Web at

http://www.hypertransport.org

PCI USB Controller

The Power Mac G5 CPU uses a PCI USB controller ASIC with one Enhanced Host Controller Interface (EHCI) function and two Open Host Controller Interface (OHCI) functions. The controller has a total of four ports available to support the internal AGP slot and three external USB ports. If connected to classic-speed USB devices, the two rear panel ports are connected to separate OHCI controllers.

These four USB ports comply with the Universal Serial Bus Specification 2.0. The USB register set complies with the EHCI and OHCI specifications. For more information, see “USB Ports.”

K2 I/O Controller

The K2 custom IC provides all the I/O functions. These functions are described in the following sections.

DMA Support

The K2 IC provides DB-DMA (descriptor-based direct memory access) support for the following I/O channels:

• Ultra ATA/100

• Communication slot interface

• I2S channel to the sound subsystem

• Serial ATA

The DB-DMA system provides a scatter-gather process based on memory-resident data structures that describe the data transfers. The DMA engine is enhanced to allow bursting of data files for improved performance.

Ethernet Controller

The K2 IC includes an Ethernet media access controller (MAC) and PHY. As a separate I/O channel on the K2 IC, it can operate at its full capacity without degrading the performance of other peripheral devices.

The MAC implements the link layer. It is connected to a PHY that is internal to K2 and provides 10Base-T/UTP, 100Base-TX, or 1000Base-TX operation over a standard twisted-pair interface. The Ethernet port is auto-sensing and self-configuring to allow use of either a cross-over or straight-through cable. The operating speed of the link is automatically negotiated by the PHY and the bridge, router, hub, switch, or other Mac or PC to which the Ethernet port is connected. For information about the port, see “Ethernet Port.”

FireWire Controllers

The K2 IC includes a FireWire controller that supports both IEEE 1394b (FireWire 800) with a maximum data rate of 800 Mbps (100 MBps) and IEEE 1394a (FireWire 400) with a maximum data rate of 400 Mbps (50 MBps). The IC is backwards-compatible with 1394a (FireWire 400). The K2 IC provides DMA (direct memory access) support for the FireWire interface.

The controller in the K2 IC implements the FireWire link layer. A physical layer IC, called a PHY, implements the electrical signaling protocol of the FireWire interface and provides the electrical signals to the ports. For more information, see “FireWire Ports.”

Interrupt Support

The interrupt controller for the Power Mac G5 system is an MPIC cell in the K2 IC. In addition to accepting K2 internal interrupt sources, the MPIC controller accepts internal interrupts from U3 and dedicated interrupt pins.

USB Interface

The K2 IC has two independent USB OHCI controllers. One is used for the optional modem module and one for the build-to-order Bluetooth interface.

The external USB interface is via the PCI USB controller; see “PCI USB Controller.”

Serial ATA Interface

Based on the Serial ATA 1.0 specification, Serial ATA (S-ATA) is a disk-interface technology that delivers up to 1.5 Gbps of performance to each independent drive bus on the Power Mac G5 computer. It provides a scalable, point-to-point connection that allows multiple ports to be aggregated into a single controller. Serial ATA uses a thin, point-to-point cable connection that enables easy routing within a system, avoiding master/slave, daisy-chaining, and termination issues and enabling better airflow within a system.

The K2 IC implements two Serial ATA revision one ports, each of which accommodates one independent internal hard drive.

For information about the drive bays, see “Hard Disk Drives.”

Ultra DMA ATA/100 Interface

In the Power Mac G5 computer, the K2 IC provides an Ultra DMA ATA/100 interface to support the optical drive. For information about specific drives, see “Disk Drives.”

Sound System Overview

The sound circuitry is connected to the K2 IC by a standard I2S (inter-IC sound) bus. The K2 IC provides DB-DMA (descriptor-based direct memory access) support for the I2S port.

The Power Mac G5 circuitry consists of two main components: an analog audio CODEC IC and a digital audio CODEC IC. The analog audio CODEC IC includes an A/D converter, a D/A converter, and digital audio processing functions. The digital audio processing functions include output equalization, dynamic range compression, and volume control. The equalization and dynamic range control functions are set to fixed values to equalize the internal speaker. Those functions are bypassed for signals sent to the audio output jacks.

The codec functions include one stereo input pair, two stereo output pairs (line out and headphone out), and one mono output that drives the internal speaker.

Stereo signals from the audio input jack are routed to an analog line input buffer that drives the internal A/D converter. The output of the A/D converter is routed to the K2 IC over the I2S bus.

Digital audio data from the K2 IC is routed to the D/A converter on the analog audio CODEC over the I2S bus. The analog audio output from the D/A is routed to separate amplifiers that drive the line output, headphone output, and internal speaker.

The digital audio CODEC IC includes an S/PDIF (Sony/Phillips Digital Interface) digital audio receiver, a sample rate converter (SRC), a phase-locked loop (PLL), and an S/PDIF digital audio transmitter.

The S/PDIF input can operate in synchronous and asynchronous modes. In synchronous mode, the PLL in the digital audio CODEC locks on to the incoming S/PDIF data rate and drives the audio system clocks in the Power Mac G5, allowing bit-accurate data processing of the S/PDIF input data. In asynchronous mode, the incoming S/PDIF data passes through the SRC, where it is converted to the output sample rate of the Power Mac G5, allowing the Power Mac G5 to play audio at a fixed output sample rate while accepting S/PDIF input data over a wide frequency range. The S/PDIF input data is routed to the K2 IC over the I2S bus.

Digital audio data from the K2 chip is routed to the S/PDIF output transmitter in the digital audio CODEC over the I2S bus. The Power Mac G5 sends and receives S/PDIF audio data over TOSLink optical connectors.

Analog audio I/O is not independent of digital audio I/O on the Power Mac G5. Audio input can come from either the line input or the S/PDIF input, but not both at the same time. Audio output can be played simultaneously on the line output, headphones output, and S/PDIF output. However, these audio streams are not independent.

For more detail on the audio, see “Audio.”

Power Controller

The power management controller in the Power Mac G5 computer is a microcontroller called the PMU99. It supports new modes of power management that provide significantly lower power consumption than previous systems. For more information, see “Power Management.”

Graphics Cards

The Power Mac G5 computer comes with a graphics card installed in the AGP 3.0 8x Pro slot. The supported graphics cards are shown below:

All graphics cards support dual displays in either extended desktop or video mirroring mode, and support digital resolutions up to 1920x1200 pixels and analog resolutions up to 1600x1200 pixels.

The display memory on the AGP card is separate from the main memory. The display memory consists of 64 or 128 MB of DDR devices configured to make a 128-bit data bus. The display memory cannot be expanded by the user.

For more information about the features of the graphics cards and the monitors they support, see “Video Monitor Ports.”

Fan Controller

The Power Mac G5 system employs advanced thermal management to keep acoustic noise to a minimum. The system is divided into discrete zones, each with independently controlled fans bringing in cool air from the front of the enclosure, directing it through ducts and exhausting it out the rear. Temperature and power consumption are monitored by the operating system which communicates with the Fan Control Unit, which in turn controls and monitors fan operation. Note that if Mac OS X is not booted, thermal management must be provided by the alternate development operating system.

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