Architecture
This chapter describes the architecture of the iMac G5. It includes information about the major components on the main logic board: the microprocessor, the other main ICs, and the buses that connect them to each other and to the I/O interfaces.
In this section:
Block Diagram and Buses
PowerPC G5 Processor
Memory Controller
HyperTransport Technology
PCI USB Controller
Shasta I/O Controller
Graphics ICs
System Management Unit
Block Diagram and Buses
The architecture of the iMac G5 is based on the PowerPC G5 microprocessor, and two custom ICs: the U3L memory controller and the Shasta I/O controller.
Figure 2-1 provides a simplified block diagram of the U3L and Shasta ICs and the buses that connect them together.
The iMac G5 has the following data buses, not counting the processor’s dedicated interface to the backside cache.
Processor bus: up to 600 MHz (running at one-third the speed of the processor), 2 unidirectional buses that deliver 64-bit data throughput connecting the processor to the U3L IC
Memory bus: 400 MHz, bus connecting the main DDR SDRAM memory to the U3L IC is 64-bit if only one DIMM is installed, two 64-bit buses if two non-identical DIMMs are installed, or 128-bit if two identical DIMMs are installed (for additional information, refer to “RAM Expansion”)
8x AGP bus: 533 MHz, 32-bit bus connecting the AGP graphics IC to the U3L IC
Internal PCI bus: 33 MHz, 32-bit bus supports the Shasta I/O controller, the boot ROM, the AirPort Extreme Card slot, and the USB controller
Serial ATA (SATA) buses: non-education configurations support 1.5 Gbps internal hard drive connector
Ultra ATA/133 bus: supports internal optical drive or hard drive. The education configuration has a factory-installed Ultra ATA/100 hard drive and no optical drive.
HyperTransport: high-speed, bidirectional, point-to-point link for integrated circuits supports bidirectional data rates up to 800 MBps
The remainder of this chapter describes the architecture of the U3L memory controller, the Shasta I/O controller IC, and the USB controller.
PowerPC G5 Processor
The PowerPC G5 used in the iMac G5 has the following features:
64-bit PowerPC implementation with 42-bit physical memory addressing
core runs at three times the bus speed
superscalar execution core supporting more than 200 in-flight instructions
two independent double-precision floating point units
Velocity Engine: 128-bit-wide vector execution unit
64K L1 instruction cache, 32K L1 data cache
built-in 512 KB backside L2 cache
two independent, unidirectional up to 600 MHz frontside buses supporting 4.8 GBps data throughput
For more information, see the reference at “PowerPC G5 Microprocessor.”
Memory Controller
The U3L custom IC provides the bridging functionality among the processor, the memory system, HyperTransport bus, and the AGP bus.
Processor Bus
The processor bus is an up to 600 MHz bus connecting the processor to the U3L IC. The bus has 32-bit wide data running in both directions. The processor has 42-bit wide addresses.
The iMac G5 system controller is built with 90-nanometer SOI technology. This point-to-point architecture provides each subsystem with dedicated bandwidth to main memory. The U3L I/O implements an independent processor interface. The processor clock rate is either 900 MHz or 1.8 GHz for the 1.8 GHz processor or 800 MHz or 1.6 GHz for the 1.6 GHz processor and connects to the I/O through the processor interface. The processor clock is derived from a PLL which multiplies the reference clock by preset intervals of 12 times.
Out-of-order completion allows the memory controller to optimize the data bus efficiency by transferring whichever data is ready, rather than having to pass data across the bus in the order the transactions were posted on the bus. This means that a fast DDR SDRAM read can pass a slow PCI read, potentially enabling the processor to do more before it has to wait on the PCI data.
Main Memory Bus
The iMac G5 main memory bus connects the main memory to the U3L IC via the 128-bit data bus. The memory modules are 400 MHz (PC3200) DDR SDRAM DIMMs. Maximum system memory is 2 GB.
Standard supported DIMM sizes are 128, 256, 512 MB, and 1 GB. The DIMMs must be unbuffered.
For more information about memory DIMMs and installation, see “RAM Expansion.”
Accelerated Graphics Port Bus
The accelerated graphics port (AGP 8x) bus is a 533 MHz, 32-bit bus connecting the AGP IC to the U3L IC. DDR data is transmitted at both edges of the clock for peak transfers of 2.1 GBps.
The AGP bus is an enhanced PCI bus with extra functionality to burst texture data and other graphics across the port up to 8 times faster than a 66 MHz PCI port. The iMac G5 computer’s AGP implementation is compatible with version 3 of the AGP specification and with the Pro version of AGP. AGP 3.0 enables deeply pipelined memory read and write operations and demultiplexing of address and data on the bus.
To further improve the performance of the AGP bus, the U3L IC supports a graphics address remapping table (GART). Because the virtual memory system organizes main memory as randomly distributed 4 KB pages, DMA transactions for more than 4 KB of data must perform scatter-gather operations. To avoid this necessity for AGP transactions, the GART is used by the AGP bridge in the U3L to translate a linear address space for AGP transactions into physical addresses in main memory.
The U3L IC also supports a DMA Address Relocation Table (DART) that provides the same functions for AGP as does the GART, except that the functions are for devices attached to HyperTransport. Most device drivers do not require special knowledge of the DART because IOKit will configure it automatically if the driver uses IOMemoryDescriptors.
For more information on the graphics IC installed in the AGP bus, refer to “Graphics ICs.”
Internal PCI Bus
An internal 33 MHz PCI bus connects the Shasta I/O controller to the boot ROM, the AirPort Extreme Card slot, and the USB controller. The U3L IC used in the iMac G5 supports the PCI write combining feature. This feature allows sequential write transactions involving the Memory Write or Memory Write and Invalidate commands to be combined into a single PCI transaction. For memory write transactions to be combined, they must be sequential, ascending, and non-overlapping PCI addresses. Placing an eieio or sync command between the write commands prevents any write combining.
HyperTransport Technology
The DDR HyperTransport is an advanced chip-to-chip communications technology that provides a high-speed, high-performance, point-to-point link for integrated circuits. HyperTransport provides a universal connection that reduces the number of buses within a system.
The HyperTransport bus between the U3L IC and the Shasta IC is 400 MHz DDR, 8 bits wide in both directions, supporting total of 800 MBps bidirectional throughput.
For more information on the HyperTransport technology, go to the World Wide Web at
PCI USB Controller
The iMac G5 CPU uses a PCI USB controller ASIC with one Enhanced Host Controller Interface (EHCI) function and two Open Host Controller Interface (OHCI) functions. The controller has a total of four ports available to support three external USB ports and the Bluetooth module.
The four USB ports comply with the Universal Serial Bus Specification 2.0. The USB register set complies with the EHCI and OHCI specifications. For more information, see “USB Ports.”
Shasta I/O Controller
The functions of the Shasta I/O controller are described in the following sections.
DMA Support
The Shasta ICs provide DB-DMA (descriptor-based direct memory access) support for the following I/O channels:
Ultra ATA/133 bus
Ethernet interface
FireWire interface
I2S channel to the sound subsystem
Serial ATA
The DB-DMA system provides a scatter-gather process based on memory-resident data structures that describe the data transfers. The DMA engine is enhanced to allow bursting of data files for improved performance.
Wireless LAN Module
The optional AirPort Extreme wireless LAN module connects via the PCI interface.
The AirPort Extreme Card wireless LAN module contains a media access controller (MAC), a digital signal processor (DSP), and a radio-frequency (RF) section. The module connects to an internal antenna.
The AirPort Extreme Card is compliant with the IEEE 802.11g standard. The card transmits and receives data at up to 54 Mbps and is compatible with Apple AirPort systems as well as other 802.11b and 802.11g Wi-Fi certified products. For information about its operation, see “AirPort Extreme Card.”
The build-to-order Bluetooth connectivity comes off the USB controller. See “Bluetooth” for more information.
Modem Slot Support
The Shasta IC supports the modem and provides DB-DMA (descriptor-based direct memory access) support for the modem slot interface. The modem is connected via an I2S interface.
The internal hardware modem is a separate module that contains a modem controller IC, a data pump, and the interface to the telephone line (DAA). For more information about the modem, see “Internal Modem.”
Boot ROM
The boot ROM consists of 1 MB of on-board flash EEPROM. The boot ROM includes the hardware-specific code and tables needed to start up the computer using Open Firmware, to load an operating system, and to provide common hardware access services.
Ethernet Controller
The Shasta IC provides the Ethernet functions and includes an Ethernet media access controller (MAC) and PHY.
The MAC implements the link layer. It is connected to a PHY that is internal to Shasta and provides 10Base-T/UTP or 100Base-TX operation over a standard twisted-pair interface. The Ethernet port is auto-sensing and self-configuring to allow use of either a cross-over or straight-through cable. The operating speed of the link is automatically negotiated by the PHY and the bridge, router, hub, switch, or other Mac or PC to which the Ethernet port is connected.
For information about the Ethernet port, see “Ethernet Port.”
FireWire Controllers
The Shasta IC provides the FireWire functions and includes a FireWire controller that supports IEEE 1394a (FireWire 400) with a maximum data rate of 400 Mbps (50 MBps). The Shasta IC provides DMA (direct memory access) support for the FireWire interface.
The controller in the Shasta IC implements the FireWire link layer. Vesta is a PHY that implements the electrical signaling protocol of the FireWire interface and provides the electrical signals to the ports.
For more information, see “FireWire 400 Ports.”
Interrupt Support
The interrupt controller for the iMac G5 system is an MPIC cell in the Shasta IC. In addition to accepting internal interrupt sources from the I/O, the MPIC controller accepts internal interrupts from U3L and dedicated interrupt pins.
Serial ATA Interface
Based on the Serial ATA 1.0 specification, Serial ATA (SATA) is a disk-interface technology that delivers up to 1.5 Gbps of performance to an independent drive bus on the iMac G5. It provides a scalable, point-to-point connection that allows multiple ports to be aggregated into a single controller. Serial ATA uses a thin, point-to-point cable connection that enables easy routing within a system, avoiding master/slave, daisy-chaining, and termination issues and enabling better airflow within a system.
For information about the drive bay, see “Hard Disk Drive.”
Ultra ATA/133 Interface
In the iMac G5 computer, the Shasta IC provides an Ultra ATA/133 interface to support an optical drive or hard drive. For information about specific drives, see “Hard Disk Drive.”
Sound System Overview
The sound circuitry is connected to the Shasta IC by a standard I2S (inter-IC sound) bus. The Shasta IC provides DB-DMA (descriptor-based direct memory access) support for the I2S port.
The iMac G5 circuitry is implemented with an analog/digital audio CODEC IC (CODEC) and supporting input/output circuitry. The CODEC includes a microphone preamp, an A/D converter, a D/A converter, and a S/PDIF (Sony/Phillips Digital Interface) digital audio transmitter.
The CODEC connects to Shasta over the I2S bus. Stereo signals from the audio input jack are routed to an analog line input amplifier that drives the internal A/D converter in the CODEC. The output of the A/D converter in the CODEC is routed to the Shasta IC over the I2S bus. Digital audio data from the Shasta IC is routed to the D/A converter in the analog CODEC over the I2S bus. The analog audio output from the D/A converter in the CODEC is routed to separate amplifiers that drive the headphones output and internal speakers.
The iMac G5 has a built-in microphone located at the bottom of the display. The analog signal from the microphone is routed to the microphone preamp in the CODEC, which is then routed to the A/D converter in the CODEC.
For more detail on the audio, see “Audio.”
Graphics ICs
The iMac G5 the graphics IC is an NVIDIA GeForce4 MX with 32 MB DDR RAM in the education configuration or an NVIDIA GeForce FX 5200 Ultra with 64 MB DDR RAM in the retail configurations. Both graphics controllers contain 2D and 3D acceleration engines, front-end and back-end scalers, a display controller, and an AGP 3.0 8x bus interface with bus master capability.
The NVIDIA GeForce4 MX supports a display size of 1440x900 pixels, with lesser resolutions scaled accordingly. The NVIDIA GeForce FX 5200 Ultra supports a display size of 1440x900 pixels for the 17” model and 1680x1050 pixels for the 20” model, with lesser resolutions scaled accordingly.
The display generated for the flat panel display is simultaneously available for an external monitor in mirror mode; see “Video Monitor Port.” For information about the display and supported resolutions, see “Flat Panel Display.” Composite video and S-video signals can be displayed on either an NTSC display or a PAL display; see “Video Display Adapter.”
System Management Unit
The iMac G5 uses an advanced system management unit (SMU) to manage the thermal and power conditions, while keeping the acoustic noise to a minimum.
The iMac G5 system employs advanced thermal and power management to keep acoustic noise to a minimum. The system brings in cool air from the bottom of the enclosure, directing it over system components and exhausting it out the top. Temperature and power consumption are monitored by the operating system which communicates with the SMU, which in turn controls and monitors fan operation. If Mac OS X is not booted, thermal management must be provided by the alternate development operating system.
Note: If Mac OS X is not booted and the alternate development operating system does not manage the fans, the fans go into an unmanaged state and run at full speed.
The SMU controls the fans in the iMac G5 and regulates the speeds to run each fan. The SMU derives fan speed from sensors, some of which monitor thermal only, while others monitor both thermal and power.
If the SMU does not receive an update from the operating system within two minutes, it begins to ramp up the speed of the fans to full speed.
© 2000, 2007 Apple Inc. All Rights Reserved. (Last updated: 2007-04-03)