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Address Allocations

The first implementation of Power Macintosh computers that uses the PCI bus reserves specific areas of the overall 32-bit address space for use by PCI expansion cards. Address allocation in the first Macintosh PCI system follows these general principles:

• A Power Macintosh system may contain up to four peer PowerPC-to-PCI host bridges. The functions of these bridges are described in PCI Host Bridge Operation.
• After each PCI host bridge, PCI-to-PCI bridges may be added in any configuration to create up to 256 PCI buses in the Power Macintosh hardware, the maximum that the PCI specification allows. However, properties that must be stored on disk or in NVRAM between system startups can be addressed only to five levels of PCI-to-PCI bridges behind each host bridge. Therefore the number of hardware PCI buses that the system software supports fully is limited to six times the number of host bridges, or 24 buses maximum.
• More than 1.8 GB of address space is allocated for PCI memory space.
• Remaining regions of the Macintosh 32-bit address space are allocated to system RAM, ROM, and control.

The general memory allocation scheme for the first implementation of Power Macintosh computers with PCI buses is shown in Table 2-1.