PCI Host Bridge Operation
The most basic function of the
PCI host bridge is to translate between PowerPC processor bus cycles and PCI bus cycles. The bridge in the first implementation of PCI on Power Macintosh provides the following features:
-
It supports asynchronous clock operation up to 50 MHz on the PowerPC bus and up to 33 MHz on the PCI bus. The system architecture in Macintosh PowerPC G3 computers supports asynchronous clock operation up to 100 MHz on the PowerPC bus and up to 66 MHz on the PCI bus.
-
It supports split-transaction PowerPC bus implementations.
-
It provides dual alternating 32-byte data transaction buffers, one set for bus master transactions initiated by the PowerPC processor bus and one set for bus master transactions initiated by the PCI bus.
-
The PowerPC bus can be used in big-endian or little-endian modes. PCI data is always little-endian, and is correctly translated by the PCI host bridge to and from the PowerPC bus in conformance to the PowerPC mode setting. Mac OS is big-endian, so the PowerPC mode setting is big-endian while running Mac OS. For information on translating big-endian and little-endian data formats, see
Addressing Modes.
-
It supports concurrent PowerPC bus and PCI bus activity.
-
Posted writes are always enabled from both PowerPC and PCI masters.
-
It supports a 32-byte cache line size.
-
It supports and optimizes for the cycle types memory read line and memory write and invalidate. The bridge also accepts memory read multiple cycles from PCI masters and treats them the same as memory read line cycles.
-
The longest burst generated as a master or accepted before disconnecting as a target is 32 bytes, the Power Macintosh cache line size.
-
It uses medium device select (
DEVSEL) timing when operating as a PCI target.
Table 1-3
lists the commands that the Macintosh PCI host bridge supports for all PCI cycle types (all encodings of lines C/BE#[3:0]). The third and fourth columns show whether the bridge can generate the cycle on the PCI bus as a master and whether it can respond to the cycle as a target.
Table 1-3
Bridge support for PCI cycle types
|
Lines
C/BE#[3:0]
|
Command
|
Supported as PCI master
|
Supported as PCI target
|
|
0000 (0x0)
|
Interrupt acknowledge
|
Yes
|
No
|
|
0001 (0x1)
|
Special cycle
|
Yes
|
No
|
|
0010 (0x2)
|
I/O read
|
Yes
|
No
|
|
0011 (0x3)
|
I/O write
|
Yes
|
No
|
|
0100 (0x4)
|
Reserved
|
n.a.
|
n.a.
|
|
0101 (0x5)
|
Reserved
|
n.a.
|
n.a.
|
|
0110 (0x6)
|
Memory read
|
Yes
|
Yes
|
|
0111 (0x7)
|
Memory write
|
Yes
|
Yes
|
|
1000 (0x8)
|
Reserved
|
n.a.
|
n.a.
|
|
1001 (0x9)
|
Reserved
|
n.a.
|
n.a.
|
|
1010 (0xA)
|
Configuration read
|
Yes
|
Yes
|
|
1011 (0xB)
|
Configuration write
|
Yes
|
Yes
|
|
1100 (0xC)
|
Memory read multiple
|
No
|
Yes
|
|
1101 (0xD)
|
Dual address cycle
|
No
|
No
|
|
1110 (0xE)
|
Memory read line
|
Yes
|
Yes
|
|
1111 (0xF)
|
Memory write and invalidate
|
Yes
|
Yes
|
PCI
memory space is supported through the bridge transparently--it requires no software abstraction layer to provide functionality. Because the PCI specification defines cycle types that are not directly supported by the PowerPC processor, the Macintosh PCI host bridge provides means to create I/O, configuration, interrupt acknowledge, and special cycles. The bridge generates these cycles in response to the system interface routines described in
PCI Nonmemory Space Cycle Generation. To ensure compatibility with future Power Macintosh computers, software must use these routines to access PCI spaces other than PCI memory space.
© 1999 Apple Computer, Inc. – (Last Updated 26 March 99)
