---

Architecture

This chapter describes the architecture of the PowerBook G4 computer. It includes information about the major components on the main logic board: the microprocessor, the other main ICs, and the buses that connect them to each other and to the I/O interfaces.

In this section:

Block Diagram and Buses
Microprocessor and Caches
Memory Controller and Bus Bridge
I/O Controller

Block Diagram and Buses

This section is an overview of the major ICs and buses on the computer’s main logic board.

Block Diagram

Figure 2-1 is a simplified block diagram of the main logic board. The diagram shows the input and output connectors, the main ICs, and the buses that connect them together.

Main ICs and Buses

The architecture of the PowerBook G4 computer is designed around the PowerPC G4 microprocessor and two custom ICs: the Uni-N memory controller and bus bridge, and the KeyLargo I/O device controller. Those three ICs occupy the center of the block diagram.

The PowerPC G4 microprocessor is connected to the Uni-N memory controller and bus bridge IC by a MaxBus bus. The bus clock speed is 133 MHz. The Uni-N IC has other buses that connect with the KeyLargo IC, the main system RAM, and the graphics IC. The buses implemented by the Uni-N IC are summarized in Table 2-1, which is in the section “Memory Controller and Bus Bridge.”

The Uni-N IC is connected to the KeyLargo I/O controller IC by a 32-bit PCI bus with a bus clock speed of 33 MHz. That bus also connects to the Boot ROM and the CardBus controller. The KeyLargo IC has other buses that connect with the hard disk drive and the optical drive, the power controller IC, the sound IC, the internal modem module, and the wireless LAN module.

Each of the components listed here is described in one of the following sections.

Microprocessor and Caches

The microprocessor communicates with the rest of the system by way of a 64-bit MaxBus bus to the Uni-N IC. The microprocessor has a separate bus to its internal second-level cache.

PowerPC G4 Microprocessor

The PowerPC G4 microprocessor used in the PowerBook G4 computer has many powerful features, including an efficient pipelined system bus called MaxBus.

Features of the PowerPC G4 include

• 32-bit PowerPC implementation

• superscalar PowerPC core

• Velocity Engine (AltiVec technology): 128-bit-wide vector execution unit

• dual 32 KB instruction and data caches

• an on-chip level 2 (L2) cache consisting of 256 KB with a clock speed ratio of 1:1

• high bandwidth MaxBus (also compatible with 60x bus)

• fully symmetric multiprocessing capability

The PowerPC G4 microprocessor in the PowerBook G4 computer runs at a clock speed of 867 MHz or 1 GHz.

Level 2 Cache

The data storage for the L2 cache consists of 256 KB of fast static RAM that is built into the microprocessor chip along with the cache controller and tag storage. The built-in L2 cache runs at the same clock speed as the microprocessor.

Level 3 Cache

The data storage for the L3 cache is 1 MB of DDR SRAM running at a clock speed ratio of 5:1. The tag storage for the L3 cache is built into the microprocessor.

Memory Controller and Bus Bridge

The Uni-N memory controller and bus bridge IC provides cost and performance benefits by combining several functions into a single IC. It contains the memory controller, the PCI bus bridge, the Ethernet and FireWire interfaces, and the AGP interface.

Each of the separate communication channels in the Uni-N IC can operate at its full capacity without degrading the performance of the other channels.

In addition to the four buses listed in Table 2-1, the Uni-N IC also has separate interfaces to the physical layer (PHY) ICs for Ethernet and FireWire, and an IIC (inter-IC control bus) interface that is used for configuring the memory subsystem.

The microprocessor and the I/O controller IC are described in their own sections. The following sections describe the other subsystems that are connected to the Uni-N IC.

System RAM

The memory subsystem in the PowerBook G4 computer supports two slots for 144-pin SO-DIMMs (small-outline dual inline memory modules). The data bus to the RAM and DIMM is 64 bits wide, and the memory interface is synchronized to the MaxBus bus interface at 133 MHz. See “RAM Expansion Slots.”

Boot ROM

The boot ROM is connected to the Uni-N IC by way of the high byte of the PCI bus plus three additional control signals: chip select, write enable, and output enable. The boot ROM is a 1 MB by 8 bit device.

FireWire Controller

The Uni-N IC includes an IEEE 1394a FireWire controller with a maximum data rate of 400 Mbits (50 MB) per second. The Uni-N IC provides DMA (direct memory access) support for the FireWire interface.

The controller in the Uni-N IC implements the FireWire link layer. A physical layer IC, called a PHY, implements the electrical signaling protocol of the FireWire interface and provides the electrical signals to the port. For more information, see “FireWire Connector.”

Ethernet Controller

The Uni-N IC includes an Ethernet media access controller (MAC) that implements the link layer. The Uni-N IC provides DB-DMA support for the Ethernet interface.

The Ethernet controller in the Uni-N IC is connected to a PHY interface IC that provides the electrical signals to the port. The PHY is capable of operating in either 10Base-T, 100Base-T, or 1000Base-T mode: The actual speed of the link is automatically negotiated by the PHY and the bridge or router to which it is connected. For more information, see “Ethernet Port.”

The PHY supports Auto-MDIX, which allows the use of straight-through cables in crossover situations (and conversely). For more information, see “Ethernet Port.”

Video Display Subsystem

The video display subsystem contains the graphics controller IC along with either 32 MB of DDR memory in the 867 MHz computer or 64 MB of DDR memory (32 MB internal and another 32 MB external to the IC) in the 1 GHz computer. The graphics IC, an ATI Mobility Radeon 9000, contains 2D and 3D acceleration engines, front-end and back-end scalers, a CRT controller, and an AGP4x bus interface with bus master capability.

The features of the Mobility Radeon 9000 include

• graphics processor clock speed of 200 MHz

• memory clock speed of 200 MHz

• support for 32 MB of DDR video memory with 64-bit interface

• support for 64 MB of DDR video memory with 128-bit interface

• 2D and 3D graphics acceleration

• transform acceleration

• lighting acceleration

• video acceleration

• support for MPEG decoding

• support for video mirror mode

• support for dual-display mode

• S-video output for a TV monitor

• support for programmable pixel and vertex shading

The interface between the graphics IC and the rest of the system is an AGP4x (accelerated graphics port, quadruple speed) bus on the Uni-N IC. To give the graphics IC fast access to system memory, the AGP bus has separate address and data lines and supports deeply pipelined read and write operations. The AGP bus has 32 data lines and a clock speed of 133 MHz.

The graphics IC uses a graphics address remapping table (GART) to translate AGP logical addresses into physical addresses. The graphics driver software can allocate memory in both the graphics SDRAM and the main memory.

The graphics IC supports the built-in flat-panel display and an external monitor. The external monitor can either mirror the built-in display or show additional desktop space (dual-display mode). For information about the displays and supported resolutions, see “Flat-Panel Display” and “External Monitors.”

I/O Controller

The I/O controller IC in the PowerBook G4 computer is a custom IC called KeyLargo. It provides the interface and control signals for the devices and functions described in the following sections.

DMA Support

The KeyLargo IC provides DB-DMA (descriptor-based direct memory access) support for the following I/O channels:

• Ultra DMA ATA interface to the the internal hard drive

• modem slot interface to the built-in modem

• IIS channel to the sound IC

The DB-DMA system provides a scatter-gather process based on memory resident data structures that describe the data transfers. The DMA engine is enhanced to allow bursting of data files for improved performance.

Interrupt Support

The KeyLargo IC has an interrupt controller (MPIC) that handles interrupts generated within the IC as well as external interrupts, such as those from the Ethernet and FireWire controllers.

USB Interface

The KeyLargo IC implements two independent USB controllers (root hubs), each of which is connected to one of the ports on the back panel of the computer. The use of two independent controllers allows both USB ports to support high data rate devices at the same time with no degradation of their performance. If a user connects a high-speed (12 Mbps) device to one port and another high-speed device to the other, both devices can operate at their full data rates.

The two external USB connectors support USB devices with data transfer rates of 1.5 Mbps or 12 Mbps. For more information about the connectors, see “USB Connectors.”

USB devices connected to the PowerBook G4 computer are required to support USB-suspend mode as defined in the USB specification. Information about the operation of USB-suspend mode on Macintosh computers is included in the Mac OS USB DDK API Reference. To obtain it, see the reference at “USB Interface.”

The USB ports on the PowerBook G4 computer comply with the Universal Serial Bus Specification 1.1 Final Draft Revision. The USB controllers comply with the Open Host Controller Interface (OHCI) specification.

Ultra DMA/66 Interface

The KeyLargo IC provides an Ultra DMA/66 channel that is connected to the internal hard disk drive. The KeyLargo IC provides DB-DMA (descriptor-based direct memory access) support for the Ultra DMA interface.

The internal hard disk drive is connected as device 0 (master) in an ATA Device 0/1 configuration.

EIDE Interface

The KeyLargo IC provides an EIDE interface (ATA bus) that supports the Combo (DVD-ROM/CD-RW) drive, SuperDrive (DVD-R/CD-RW) drive, and the wireless LAN module. The Combo and SuperDrive drives are ATAPI drives and are device-selected as master in an ATA device configuration.

Modem Support

The internal modem is connected to an internal USB port. The KeyLargo IC provides DB-DMA support for the modem interface. The modem provides digital call progress signals to the Snapper sound circuitry.

The internal modem is a separate module that contains the data pump IC and the interface to the telephone line (DAA). For more information about the modem, see “Internal Modem.”

Sound Circuitry

The sound circuitry, called Snapper, is connected to the KeyLargo IC by a standard IIS (inter-IC sound) bus. The KeyLargo IC provides DB-DMA (descriptor-based direct memory access) support for the IIS port.

The Snapper circuitry includes a signal processing IC that handles the equalization and volume control functions, a codec IC that performs A-to-D and D-to-A conversion, and a power amplifier that drives the headphone jack.

All audio is handled digitally inside the computer. The Snapper circuitry performs digital-to-analog conversion for the audio signals to the internal speakers and the headphone jack.

For a description of the features of the sound system, see “Sound System.”

Power Controller

The PowerBook G4 computer can operate from a 15 volt power outlet on an airline, but for safety reasons, the computer will not allow battery charging. In order for the computer to detect the connection to airline power, the airline power cable should have a sense resistor of 24.3K ohms connected between the power plug's shell and ground.

The PowerBook G4 computer has a new variable speed fan control circuit and a new thermal circuit that will force the unit to sleep if the processor temperature exceeds 85 degrees Celsius. The circuit remains active during sleep so that it can continue to poll the temperature.

The power management controller in the PowerBook G4 computer is a custom IC called the PMU99. It supports several power-saving modes of operation, including idle, doze, and sleep. For more information, see “Power-Saving Features.”

AirPort Card Interface

The interface between the AirPort Card and the KeyLargo IC uses the same data bus as the optical drive but has its own control signals.

The AirPort Card contains a media access controller (MAC), a digital signal processor (DSP), and a radio-frequency (RF) section. The card has a connector for the cable to the antennas.

Two antennas are built into the computer’s case. To improve reception, a diversity module between the antennas and the card measures the signal strength from both antennas and selects the stronger signal for the AirPort Card.

The design of the AirPort Card is based on the IEEE 802.11 standard. The card transmits and receives data at up to 11 Mbps and is compatible with older systems that operate at 1 or 2 Mbps. For information about its operation, see “AirPort Card.”

CardBus Controller IC

The interface to the PC Card slot is connected to the PCI bus. The CardBus controller IC is a PCI1410A device made by Texas Instruments. It supports both 16-bit PC Cards and 32-bit CardBus Cards.

---